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V1.0.6

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刘可亮
2024-09-03 11:16:08 +08:00
parent cf270df8d6
commit 803cac77d5
2931 changed files with 614364 additions and 31222 deletions
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4
bsp/artinchip/hal/cmu/aic_hal_pll_clk.c
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022, Artinchip Technology Co., Ltd
* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -279,7 +279,7 @@ static int clk_pll_set_rate(struct aic_clk_comm_cfg *comm_cfg,
PLL_SDM_AMP_MAX / ppm_max;
/* SDM uses triangular wave, 33KHz by default */
sdm_step = (PLL_SDM_AMP_MAX - sdm_amp) * 2 *
sdm_step = (u64)(PLL_SDM_AMP_MAX - sdm_amp) * 2 *
PLL_SDM_SPREAD_FREQ;
do_div(sdm_step, parent_rate);
if (sdm_step > 511)