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V1.0.6

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This commit is contained in:
刘可亮
2024-09-03 11:16:08 +08:00
parent cf270df8d6
commit 803cac77d5
2931 changed files with 614364 additions and 31222 deletions
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1
bsp/artinchip/include/drv/aic_drv_gpio.h
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@@ -18,6 +18,7 @@ void drv_pin_drive_set(unsigned int pin, unsigned int strength);
void drv_pin_mux_set(unsigned int pin, unsigned int func);
unsigned int drv_pin_mux_get(unsigned int pin);
long drv_pin_get(const char *name);
int drv_pin_init(void);
#ifdef __cplusplus
}

4
bsp/artinchip/include/drv/aic_drv_wdt.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022-2023, ArtInChip Technology Co., Ltd
* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -16,5 +16,5 @@
#define RT_DEVICE_CTRL_WDT_SET_RST_CPU (RT_DEVICE_CTRL_BASE(WDT) + 11)
#define RT_DEVICE_CTRL_WDT_SET_RST_SYS (RT_DEVICE_CTRL_BASE(WDT) + 12)
#define RT_DEVICE_CTRL_WDT_GET_RST_EN (RT_DEVICE_CTRL_BASE(WDT) + 13)
#define RT_DEVICE_CTRL_WDT_EN_REG (RT_DEVICE_CTRL_BASE(WDT) + 14)
#endif /* _AIC_DRV_WDT_H_ */

4
bsp/artinchip/include/drv/drv_dvp.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022-2023, ArtInChip Technology Co., Ltd
* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -51,6 +51,8 @@ int aic_dvp_q_buf(u32 index);
int aic_dvp_dq_buf(u32 *pindex);
int aic_dvp_probe(void);
int aic_dvp_vb_init(void);
void aic_dvp_vb_deinit(void);
int aic_dvp_open(void);
int aic_dvp_close(void);

11
bsp/artinchip/include/drv/fal_cfg.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2023, Artinchip Technology Co., Ltd
* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -17,11 +17,20 @@
/* ===================== Flash device Configuration ========================= */
extern struct fal_flash_dev nor_flash0;
extern struct fal_flash_dev nor_flash1;
/* flash device table */
#if defined(AIC_QSPI1_DEVICE_SPINOR)
#define FAL_FLASH_DEV_TABLE \
{ \
&nor_flash0, \
&nor_flash1, \
}
#else
#define FAL_FLASH_DEV_TABLE \
{ \
&nor_flash0, \
}
#endif
#endif /* _FAL_CFG_H_ */

22
bsp/artinchip/include/drv/pm_cfg.h
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@@ -1,3 +1,10 @@
/*
* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
* Authors: dwj <weijie.ding@artinchip.com>
*/
#ifndef _PM_CFG_H_
#define _PM_CFG_H_
@@ -34,7 +41,16 @@ enum pm_module_id {
PM_MODULE_MAX_ID, /* enum must! */
};
extern rt_timer_t touch_timer;
extern volatile uint8_t wakeup_triggered;
#ifdef AIC_USING_PM
void rt_pm_set_pin_wakeup_source(rt_base_t pin);
void rt_pm_clear_pin_wakeup_source(rt_base_t pin);
void rt_pm_disable_pin_irq_nonwakeup(void);
void rt_pm_resume_pin_irq(void);
#else
static inline void rt_pm_set_pin_wakeup_source(rt_base_t pin) {}
static inline void rt_pm_clear_pin_wakeup_source(rt_base_t pin) {}
static inline void rt_pm_disable_pin_irq_nonwakeup(void) {}
static inline void rt_pm_resume_pin_irq(void) {}
#endif
#endif
#endif

5
bsp/artinchip/include/drv_bare/aic_drv_bare.h
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@@ -1,7 +1,9 @@
/*
* Copyright (c) 2022, Artinchip Technology Co., Ltd
* Copyright (c) 2024, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
* Authors: Weihui.Xu <weihui.xu@artinchip.com>
*/
#ifndef _ARTINCHIP_AIC_DRV_BARE_H_
@@ -18,6 +20,7 @@ extern "C" {
#include "heap.h"
#include "aic_stdio.h"
#include "console.h"
#include "drv_rtc.h"
#include "uart.h"
#include "mmc.h"
#include "mtd.h"

68
bsp/artinchip/include/drv_bare/drv_rtc.h Normal file
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@@ -0,0 +1,68 @@
/*
* Copyright (c) 2024, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
* Authors: Weihui.Xu <weihui.xu@artinchip.com>
*/
#ifndef _DRV_RTC_H_
#define _DRV_RTC_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdio.h>
#include <aic_core.h>
#define RTC_OK 0
#define RTC_ERR (-1)
#define RTC_NULL 0
/* days per month -- nonleap! */
static const short __spm[13] =
{
0,
(31),
(31 + 28),
(31 + 28 + 31),
(31 + 28 + 31 + 30),
(31 + 28 + 31 + 30 + 31),
(31 + 28 + 31 + 30 + 31 + 30),
(31 + 28 + 31 + 30 + 31 + 30 + 31),
(31 + 28 + 31 + 30 + 31 + 30 + 31 + 31),
(31 + 28 + 31 + 30 + 31 + 30 + 31 + 31 + 30),
(31 + 28 + 31 + 30 + 31 + 30 + 31 + 31 + 30 + 31),
(31 + 28 + 31 + 30 + 31 + 30 + 31 + 31 + 30 + 31 + 30),
(31 + 28 + 31 + 30 + 31 + 30 + 31 + 31 + 30 + 31 + 30 + 31),
};
/* seconds per day */
#define SPD (24 * 60 * 60)
/* used for alarm function */
struct rtc_wkalarm
{
bool enable; /* 0 = alarm disabled, 1 = alarm enabled */
int tm_sec; /* alarm at tm_sec */
int tm_min; /* alarm at tm_min */
int tm_hour; /* alarm at tm_hour */
};
void tz_set(char tz);
char tz_get(void);
time_t timegm(struct tm * const t);
struct tm *gmtime_bare(const time_t *timep, struct tm *r);
int rtc_get_secs(time_t *sec);
int rtc_set_secs(time_t *sec);
int rtc_get_alarm(struct rtc_wkalarm *alarm);
int rtc_set_alarm(struct rtc_wkalarm *alarm);
struct tm* get_localtime(void);
char *local_time(void);
int drv_rtc_init(void);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_RTC_H_ */

3
bsp/artinchip/include/drv_bare/mmc.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2023, Artinchip Technology Co., Ltd
* Copyright (c) 2022-2024, Artinchip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -17,6 +17,7 @@ struct aic_sdmc_pdata {
ulong base;
int irq;
int clk;
int clk_freq;
u32 is_sdio;
u8 id;
u8 buswidth;

4
bsp/artinchip/include/drv_bare/mtd.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2023, Artinchip Technology Co., Ltd
* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -86,7 +86,7 @@ int mtd_write_oob(struct mtd_dev *mtd, u32 offset, u8 *data, u32 len,
u8 *spare_data, u32 spare_len);
int mtd_block_isbad(struct mtd_dev *mtd, u32 offset);
int mtd_block_markbad(struct mtd_dev *mtd, u32 offset);
struct mtd_partition *mtd_parts_parse(char *parts);
struct mtd_partition *mtd_parts_parse(char *parts, u32 spi_bus);
void mtd_parts_free(struct mtd_partition *head);
int mtd_contread(struct mtd_dev *mtd, u32 offset, u8 *data, u32 len);

5
bsp/artinchip/include/hal/aic_hal_can.h
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@@ -123,6 +123,9 @@
#define CAN_TSEG_MIN 7
#define CAN_ERRP_THRESHOLD 127
#define CAN_BUS_ERRCODE_CRCERRCNT 13
#define CAN_BUS_ERRCODE_ACKERRCNT 15
typedef enum {
ACTIVE_STATUS,
WARNING_STATUS,
@@ -180,6 +183,8 @@ typedef struct can_status {
u32 othererrcnt;
u32 recvpkgcnt;
u32 sndpkgcnt;
u32 ackerrcnt;
u32 crcerrcnt;
u32 rxerr;
u32 txerr;
} can_status_t;

6
bsp/artinchip/include/hal/aic_hal_de.h
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2020-2022 ArtInChip Technology Co., Ltd.
* Copyright (C) 2020-2024 ArtInChip Technology Co., Ltd.
* Authors: Ning Fang <ning.fang@artinchip.com>
*
* SPDX-License-Identifier: Apache-2.0
@@ -133,6 +133,8 @@ enum de_qos_plane {
#define SCALER0_CTRL_BILINEAR_SELECT BIT(2)
#define SCALER0_CTRL_EN BIT(0)
#define SCALER0_CTRL_ACTIVE BIT(4)
#define SCALER0_INPUT_SIZE_SET(w, h) ((((h) & 0x1fff) << 16) \
| (((w) & 0x1fff) << 0))
@@ -443,6 +445,8 @@ void de_ui_layer_rect_enable(void *base_addr, u32 index, u32 enable);
void de_set_scaler0_channel(void *base_addr, u32 input_w, u32 input_h,
u32 output_w, u32 output_h, u32 channel);
void de_scaler0_active_handle(void *base_addr, u32 index);
void de_scaler0_enable(void *base_addr, u32 enable);
/**

3
bsp/artinchip/include/hal/aic_hal_gpio.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022, Artinchip Technology Co., Ltd
* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -90,6 +90,7 @@ int hal_gpio_toggle_output(unsigned int group, unsigned int pin);
int hal_gpio_enable_irq(unsigned int group, unsigned int pin);
int hal_gpio_disable_irq(unsigned int group, unsigned int pin);
int hal_gpio_group_get_irq_en(unsigned int group, unsigned int *pen);
int hal_gpio_group_set_irq_en(unsigned int group, unsigned int en);
int hal_gpio_group_get_irq_stat(unsigned int group, unsigned int *pstat);
int hal_gpio_group_set_irq_stat(unsigned int group, unsigned int stat);
int hal_gpio_get_irq_stat(unsigned int group, unsigned int pin,

9
bsp/artinchip/include/hal/aic_hal_uart.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022, Artinchip Technology Co., Ltd
* Copyright (c) 2022-2024, Artinchip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -89,6 +89,7 @@ extern "C" {
#define AIC_UART_232_SUSPEND_DATA 0x84
#define AIC_UART_SW_FLOW_CTRL 0x85
#define AIC_UART_SW_RECEIVE_ON_OFF 0x86
#define AIC_UART_SET_BAUDRATE 0x87
#define AIC_UART_DEV_MODE_RS485 0x1
@@ -233,7 +234,8 @@ typedef struct
typedef enum
{
USART_INTR_WRITE,
USART_INTR_READ
USART_INTR_READ,
USART_INTR_ELSI,
} usart_intr_type_e;
/**
@@ -616,6 +618,8 @@ int32_t hal_usart_config_rs485(usart_handle_t handle, bool rs485, bool compactio
int32_t hal_usart_rts_ctl_soft_mode_set(usart_handle_t handle);
int32_t hal_usart_rts_ctl_soft_mode_clr(usart_handle_t handle);
int32_t hal_usart_halt_tx_enable(usart_handle_t handle, uint8_t halt_tx_enable);
void hal_usart_intr_recv_line(int32_t idx, aic_usart_priv_t *usart_priv);
void hal_usart_clear_rxfifo(usart_handle_t handle);
#if defined (RT_SERIAL_USING_DMA)
int32_t hal_uart_set_fifo(usart_handle_t handle);
@@ -624,7 +628,6 @@ int32_t hal_usart_rx_enable_drq(usart_handle_t handle);
int32_t hal_usart_tx_disable_drq(usart_handle_t handle);
int32_t hal_usart_rx_disable_drq(usart_handle_t handle);
int32_t hal_usart_get_rx_fifo_num(usart_handle_t handle);
int32_t hal_usart_set_ier(usart_handle_t handle, uint8_t enable);
int32_t hal_usart_set_hsk(usart_handle_t handle);
int32_t hal_uart_rx_dma_config(usart_handle_t handle, uint8_t *buf, uint32_t size);
int32_t hal_uart_send_by_dma(usart_handle_t handle, uint8_t *buf, uint32_t size);

7
bsp/artinchip/include/hal/bouncebuf.h
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@@ -1,9 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Generic bounce buffer implementation
*
* Copyright (C) 2012 Marek Vasut <marex@denx.de>
*/
/* SPDX-License-Identifier: Apache-2.0 */
#ifndef __INCLUDE_BOUNCEBUF_H__
#define __INCLUDE_BOUNCEBUF_H__

4
bsp/artinchip/include/hal/hal_adcim.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022-2023, ArtInChip Technology Co., Ltd
* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -14,7 +14,7 @@
int hal_adcim_calibration_set(unsigned int val);
s32 hal_adcim_probe(void);
u32 hal_adcim_auto_calibration(void);
int hal_adcim_adc2voltage(int val, u32 cal_data, int scale, float def_voltage);
int hal_adcim_adc2voltage(u16 *val, u32 cal_data, int scale, float def_voltage);
#ifdef AIC_ADCIM_DM_DRV
void hal_dm_chan_show(void);

4
bsp/artinchip/include/hal/hal_audio_reg.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022-2023, ArtInChip Technology Co., Ltd
* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -99,9 +99,11 @@
#define TX_SDM_CH0_MASK TX_SDM_CH0_EN
#define TX_PWM_CTRL_REG (0x2C)
#define TX_PDM1_EN BIT(6)
#define TX_PWM1_DIFEN BIT(5)
#define TX_PWM1_EN BIT(4)
#define TX_PWM1_MASK (3 << 4)
#define TX_PDM0_EN BIT(2)
#define TX_PWM0_DIFEN BIT(1)
#define TX_PWM0_EN BIT(0)
#define TX_PWM0_MASK (3)

4
bsp/artinchip/include/hal/hal_cap.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022-2023, ArtInChip Technology Co., Ltd
* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -31,6 +31,7 @@
struct aic_cap_data {
u8 id;
u8 flt_sel;
u32 freq;
float duty;
};
@@ -44,6 +45,7 @@ u32 hal_cap_is_pending(u32 ch);
int hal_cap_set_freq(u32 ch, u32 freq);
int hal_cap_set_cnt(u32 ch, u32 cnt);
int hal_cap_get(u32 ch);
void hal_cap_in_flt_sel(u32 ch, u8 flt_sel);
int hal_cap_in_config(u32 ch);
u32 hal_cap_reg0(u32 ch);
u32 hal_cap_reg1(u32 ch);

19
bsp/artinchip/include/hal/hal_ce.h
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@@ -1,9 +1,9 @@
/*
* Copyright (c) 2022-2023, ArtInChip Technology Co., Ltd
* Copyright (C) 2020-2024 Artinchip Technology Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Authors: Xiong Hao <hao.xiong@artinchip.com>
* Authors: Xiong Hao <hao.xiong@artinchip.com>
*/
#ifndef _AIC_HAL_CE_H_
@@ -11,6 +11,8 @@
#include <aic_common.h>
#define DEBUG_CE 0
#define RSA2048_SIGN_LEN 256
#define RSA2048_KEY_LEN 256
#define SHA256_BYTE_LEN 32
@@ -84,9 +86,9 @@
#define BE_SHA512_H6 0x6bbd41fbabd9831fULL
#define BE_SHA512_H7 0x79217e1319cde05bULL
#define ALG_UNIT_SYMM (0)
#define ALG_UNIT_HASH (1)
#define ALG_UNIT_ASYM (2)
#define ALG_SK_ACCELERATOR (0)
#define ALG_HASH_ACCELERATOR (1)
#define ALG_AK_ACCELERATOR (2)
#define ALG_DIR_ENCRYPT (0)
#define ALG_DIR_DECRYPT (1)
@@ -138,6 +140,9 @@
#define CE_KEY_SRC_PSK2 (6)
#define CE_KEY_SRC_PSK3 (7)
#define SECURE_SRAM_SIZE (1024)
#define SECURE_SRAM_BASE (0x10021000)
#define uaddr u64
#define PTR2U32(ptr) ((u32)(uaddr)(ptr))
@@ -291,15 +296,19 @@ struct crypto_task {
s32 hal_crypto_init(void);
s32 hal_crypto_deinit(void);
void hal_crypto_dump_reg(void);
void hal_crypto_irq_handler();
void hal_crypto_irq_enable(u32 alg_unit);
s32 hal_crypto_start_symm(struct crypto_task *task);
s32 hal_crypto_start_asym(struct crypto_task *task);
s32 hal_crypto_start_hash(struct crypto_task *task);
bool hal_crypto_is_start();
u32 hal_crypto_poll_finish(u32 alg_unit);
void hal_crypto_pending_clear(u32 alg_unit);
u32 hal_crypto_get_err(u32 alg_unit);
s32 hal_crypto_bignum_byteswap(u8 *bn, u32 len);
s32 hal_crypto_bignum_le2be(u8 *src, u32 slen, u8 *dst, u32 dlen);
s32 hal_crypto_bignum_be2le(u8 *src, u32 slen, u8 *dst, u32 dlen);
void hal_crypto_dump_task(struct crypto_task *task, int len);
#endif

1
bsp/artinchip/include/hal/hal_cir.h
View File

@@ -11,7 +11,6 @@
#define AIC_IR_DEV "aic-ir"
#define DEFAULT_FREQ 38000
#define US_PER_SEC 1000000UL
/* Register definition */
#define CIR_MCR_REG 0x00

50
bsp/artinchip/include/hal/hal_dvp.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022, ArtInChip Technology Co., Ltd
* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -50,21 +50,31 @@
#define DVP_CTL_EN BIT(0)
#define DVP_IRQ_EN_UPDATE_DONE BIT(7)
#define DVP_IRQ_EN_HNUM BIT(2)
#define DVP_IRQ_EN_FRAME_DONE BIT(1)
#define DVP_IRQ_STA_UPDATE_DONE BIT(7)
#define DVP_IRQ_STA_XY_CODE_ERR BIT(6)
#define DVP_IRQ_STA_FIFO_FULL BIT(3)
#define DVP_IRQ_STA_BUF_FULL BIT(3)
#define DVP_IRQ_STA_HNUM BIT(2)
#define DVP_IRQ_STA_FRAME_DONE BIT(1)
#define DVP_IRQ_CFG_HNUM_MASK GENMASK(30, 16)
#define DVP_IRQ_CFG_HNUM_SHIFT 16
#define DVP_IN_CFG_FILED_POL_NORMAL BIT(3)
#define DVP_IN_CFG_VSYNC_POL_ACTIVE_HIGH BIT(2)
#define DVP_IN_CFG_FILED_POL_ACTIVE_LOW BIT(3)
#define DVP_IN_CFG_VSYNC_POL_FALLING BIT(2)
#define DVP_IN_CFG_HREF_POL_ACTIVE_HIGH BIT(1)
#define DVP_IN_CFG_PCLK_POL_RISING_EDGE BIT(0)
#define DVP_IN_CFG_PCLK_POL_FALLING BIT(0)
/* The field definition of IN_HOR_SIZE */
#define DVP_IN_HOR_SIZE_IN_HOR_MASK GENMASK(30, 16)
#define DVP_IN_HOR_SIZE_IN_HOR_SHIFT (16)
#define DVP_IN_HOR_SIZE_XY_CODE_ERR_MASK GENMASK(15, 8)
#define DVP_IN_HOR_SIZE_XY_CODE_ERR_SHIFT (8)
#define DVP_IN_HOR_SIZE_XY_CODE_MASK GENMASK(7, 0)
#define DVP_IN_HOR_SIZE_XY_CODE_SHIFT (0)
#define DVP_IN_HOR_SIZE_XY_CODE_F BIT(6)
#define DVP_OUT_HOR_NUM(w) (((w) * 2 - 1) << 16)
#define DVP_OUT_VER_NUM(h) (((h) - 1) << 16)
@@ -119,6 +129,7 @@ struct aic_dvp_config {
enum dvp_input input;
enum dvp_input_yuv_seq input_seq;
u32 flags;
u32 interlaced;
/* Output format */
enum dvp_output output;
@@ -129,17 +140,22 @@ struct aic_dvp_config {
};
/* Some API of register, Defined in hal_dvp.c */
void aich_dvp_enable(int enable);
void aich_dvp_capture_start(void);
void aich_dvp_capture_stop(void);
void aich_dvp_clr_fifo(void);
int aich_dvp_clr_int(void);
void aich_dvp_enable_int(int enable);
void aich_dvp_set_pol(u32 flags);
void aich_dvp_set_cfg(struct aic_dvp_config *cfg);
void aich_dvp_update_buf_addr(dma_addr_t y, dma_addr_t uv);
void aich_dvp_update_ctl(void);
void aich_dvp_record_mode(void);
void aich_dvp_qos_cfg(u32 high, u32 low, u32 inc_thd, u32 dec_thd);
void hal_dvp_enable(struct aic_dvp_config *cfg, int enable);
void hal_dvp_capture_start(void);
void hal_dvp_capture_stop(void);
void hal_dvp_clr_fifo(void);
int hal_dvp_clr_int(void);
void hal_dvp_enable_int(struct aic_dvp_config *cfg, int enable);
void hal_dvp_set_pol(u32 flags);
void hal_dvp_set_cfg(struct aic_dvp_config *cfg);
void hal_dvp_update_buf_addr(dma_addr_t y, dma_addr_t uv, u32 offset);
void hal_dvp_update_ctl(void);
void hal_dvp_record_mode(void);
void hal_dvp_qos_cfg(u32 high, u32 low, u32 inc_thd, u32 dec_thd);
u32 hal_dvp_get_current_xy(void);
u32 hal_dvp_is_top_field(void);
u32 hal_dvp_is_bottom_field(void);
void hal_dvp_field_tag_clr(void);
#endif /* _ARTINCHIP_HAL_DVP_H_ */

8
bsp/artinchip/include/hal/hal_epwm.h
View File

@@ -1,9 +1,9 @@
/*
* Copyright (c) 2022-2023, ArtInChip Technology Co., Ltd
* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
* Authors: matteo <duanmt@artinchip.com>
* Authors: zrq <ruiqi.zheng@artinchip.com>
*/
#ifndef _ARTINCHIP_HAL_EPWM_H_
@@ -18,7 +18,6 @@
#else
#define EPWM_CLK_RATE 200000000 /* 200 MHz */
#endif
#define EPWM_TB_CLK_RATE 25000000 /* 25 MHz */
#define EPWM_INT_FLG BIT(0)
@@ -58,8 +57,9 @@ struct aic_epwm_arg {
u16 available;
u16 id;
enum aic_epwm_mode mode;
u32 clk_rate;
u32 tb_clk_rate;
u32 freq;
float freq;
struct aic_epwm_action action0;
struct aic_epwm_action action1;
u32 period;

4
bsp/artinchip/include/hal/hal_gpai.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022-2023, ArtInChip Technology Co., Ltd
* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -63,7 +63,7 @@ struct aic_gpai_ch {
enum aic_gpai_obtain_data_mode obtain_data_mode;
u32 smp_period;
u32 pclk_rate;
u16 latest_data;
u16 avg_data;
u16 fifo_data[AIC_GPAI_FIFO_MAX_DEPTH];
u8 fifo_valid_cnt;
u8 fifo_depth;

4
bsp/artinchip/include/hal/hal_rtc.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022-2023, ArtInChip Technology Co., Ltd
/*
* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*

11
bsp/artinchip/include/hal/hal_sdmc.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022-2023, ArtInChip Technology Co., Ltd
* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -12,11 +12,6 @@
#include <bouncebuf.h>
#define SDMC_CLOCK_MIN 400000 /* 400KHz */
#ifdef FPGA_BOARD_ARTINCHIP
#define SDMC_CLOCK_MAX 48000000 /* 48MHz */
#else
#define SDMC_CLOCK_MAX 100000000 /* 100MHz */
#endif
#define FIFO_MIN 8
#define FIFO_MAX 4096
@@ -109,6 +104,10 @@
#define SDMC_CTYPE_8BIT (0x2)
#define SDMC_CTYPE_RESERVED (0x3)
/* Data-rate */
#define SDMC_SDR_MODE (0)
#define SDMC_DDR_MODE (0x1)
/* Interrupt status & enable register defines */
#define SDMC_INT_ALL 0xffffffff
#define SDMC_INT_FROM_SDIO BIT(16)

4
bsp/artinchip/include/hal/sha1.h → bsp/artinchip/include/hal/hal_sha1.h
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@@ -1,5 +1,5 @@
#ifndef SHA1_H
#define SHA1_H
#ifndef HAL_SHA1_H
#define HAL_SHA1_H
#include <hash.h>

4
bsp/artinchip/include/hal/sha224.h → bsp/artinchip/include/hal/hal_sha224.h
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@@ -1,5 +1,5 @@
#ifndef SHA224_H
#define SHA224_H
#ifndef HAL_SHA224_H
#define HAL_SHA224_H
#include <hash.h>

4
bsp/artinchip/include/hal/sha256.h → bsp/artinchip/include/hal/hal_sha256.h
View File

@@ -1,5 +1,5 @@
#ifndef SHA256_H
#define SHA256_H
#ifndef HAL_SHA256_H
#define HAL_SHA256_H
#include <hash.h>

1
bsp/artinchip/include/hal/hal_spienc.h
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@@ -25,6 +25,7 @@
int hal_spienc_init(void);
void hal_spienc_set_cfg(u32 spi_bus, u32 addr, u32 cpos, u32 clen);
void hal_spienc_set_bypass(int status);
void hal_spienc_select_tweak(int select);
void hal_spienc_start(void);
void hal_spienc_stop(void);
int hal_spienc_check_empty(void);

6
bsp/artinchip/include/hal/hal_wdt.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022-2023, ArtInChip Technology Co., Ltd
* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -22,6 +22,9 @@ extern "C" {
#define WDT_MIN_TIMEOUT 1
#define WDT_DEFAULT_TIMEOUT 10
#define WREG_PROTECT_EN 1
#define WREG_PROTECT_DIS 0
#ifdef AIC_WDT_DRV_V11
#define RST_CPU 1
#define RST_SYS 0
@@ -49,6 +52,7 @@ void hal_wdt_thd_get(u32 ch, struct aic_wdt *wdt);
int hal_wdt_clr_int(void);
void hal_wdt_status_show(u32 ch);
void hal_wdt_reg_protect(u8 enable);
#ifdef AIC_WDT_DRV_V11
void hal_wdt_rst_type_set(u32 rst);

65
bsp/artinchip/include/hal/hal_wri.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2023, ArtInChip Technology Co., Ltd
* Copyright (c) 2023-2024, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -11,9 +11,52 @@
#include "aic_common.h"
/* Register of WRI */
#define WRI_RST_FLAG (WRI_BASE + 0x0)
#define WRI_BOOT_INFO (WRI_BASE + 0x100)
#define WRI_SYS_BAK (WRI_BASE + 0x104)
#define WRI_VERSION (WRI_BASE + 0xFFC)
#if defined(AIC_WRI_DRV_V12)
#define REG_BOOT_INFO WRI_BOOT_INFO
#define GET_REG_STATUS(c) readl(c)
#define BOOT_INFO_SET(val, mask, shift, cur) writel_bits(val, mask, shift, REG_BOOT_INFO)
#define BOOT_INFO_GET(mask, shift, cur) ({ cur = readl_bits(mask, shift, REG_BOOT_INFO); })
#define BOOT_INFO_WRITEB(cur) writel(cur, REG_BOOT_INFO)
#else
#define RTC_WR_EN_KEY 0xAC
#define RTC_REG_WR_EN (0x00FC)
#define RTC_BOOT_INFO (RTC_BASE + 0x100)
#define REG_BOOT_INFO RTC_BOOT_INFO
#define RTC_WRITE_ENABLE writeb(RTC_WR_EN_KEY, RTC_BASE + RTC_REG_WR_EN)
#define RTC_WRITE_DISABLE writeb(0, RTC_BASE + RTC_REG_WR_EN)
#define GET_REG_STATUS(c) readb(c)
#define BOOT_INFO_WRITEB(cur) \
({ \
RTC_WRITE_ENABLE; \
writeb((cur) & 0xFF, REG_BOOT_INFO); \
RTC_WRITE_DISABLE; \
})
#define BOOT_INFO_SET(val, mask, shift, cur) \
({ \
setbits(val, mask, shift, cur); \
BOOT_INFO_WRITEB(cur); \
})
#define BOOT_INFO_GET(mask, shift, cur) \
({ \
cur = readb(REG_BOOT_INFO); \
cur = getbits(mask, shift, cur); \
})
#endif
#define WRI_REBOOT_REASON_MASK GENMASK(7, 4)
#define WRI_REBOOT_REASON_SHIFT 4
#if defined(AIC_WRI_DRV_V12) || defined(AIC_WRI_DRV_V11) || defined(AIC_WRI_DRV_V10)
enum aic_warm_reset_type {
WRI_TYPE_POR = 0,
WRI_TYPE_ERR = 0,
WRI_TYPE_POR = WRI_TYPE_ERR,
WRI_TYPE_RTC,
WRI_TYPE_EXT,
WRI_TYPE_DM,
@@ -26,7 +69,8 @@ enum aic_warm_reset_type {
#if defined(AIC_WRI_DRV_V13)
enum aic_warm_reset_type {
WRI_TYPE_VDD11_SP_POR = 0,
WRI_TYPE_ERR = 0,
WRI_TYPE_VDD11_SP_POR = WRI_TYPE_ERR,
WRI_TYPE_VDD11_SW_POR,
WRI_TYPE_VDD11_C908_POR,
WRI_TYPE_RTC_POR,
@@ -51,9 +95,18 @@ enum aic_warm_reset_type {
};
#endif
struct aic_wri_ops {
u32 *wri_bit;
enum aic_warm_reset_type (*reset_type)(enum aic_warm_reset_type hw);
void (*hw_reboot_action)(enum aic_warm_reset_type hw);
void (*sw_reboot_reason)(enum aic_reboot_reason sw,
enum aic_reboot_reason r);
int (*hw_reboot_reason)(enum aic_warm_reset_type hw,
enum aic_reboot_reason *r, u32 sw);
};
extern const struct aic_wri_ops wri_ops;
enum aic_warm_reset_type aic_wr_type_get(void);
enum aic_reboot_reason aic_judge_reboot_reason(enum aic_warm_reset_type hw,
u32 sw);
void aic_clr_reboot_reason(void);
enum aic_reboot_reason aic_judge_reboot_reason(enum aic_warm_reset_type hw, u32 sw);
#endif

5
bsp/artinchip/include/hal/spienc.h
View File

@@ -26,6 +26,11 @@ static inline void spienc_set_bypass(int status)
hal_spienc_set_bypass(status);
}
static inline void spienc_select_tweak(int select)
{
hal_spienc_select_tweak(select);
}
static inline void spienc_start(void)
{
hal_spienc_start();

5
bsp/artinchip/include/uapi/mpp_types.h
View File

@@ -145,6 +145,11 @@ enum mpp_mbus_type {
/* Media bus format */
enum mpp_mbus_fmt {
MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE = 0x1001,
MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE = 0x1002,
MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE = 0x1003,
MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE = 0x1004,
MEDIA_BUS_FMT_RGB565_2X8_BE = 0x1007,
MEDIA_BUS_FMT_RGB565_2X8_LE = 0x1008,
/* YUV (including grey) */