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V1.0.6

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This commit is contained in:
刘可亮
2024-09-03 11:16:08 +08:00
parent cf270df8d6
commit 803cac77d5
2931 changed files with 614364 additions and 31222 deletions
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8
bsp/artinchip/sys/d21x/aic_drv_irq.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022, Artinchip Technology Co., Ltd
* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -11,12 +11,6 @@
extern void Default_Handler(void);
extern void SysTick_Handler(void);
#ifdef AIC_GPIO_IRQ_DRV_EN
#define MAX_IRQ_ENTRY (MAX_IRQn+GPIO_MAX_PIN)
#else
#define MAX_IRQ_ENTRY (MAX_IRQn)
#endif
void * g_irqvector[MAX_IRQ_ENTRY];
void * g_irqdata[MAX_IRQ_ENTRY];
u32 g_irqcnt[MAX_IRQ_ENTRY] = {0};

11
bsp/artinchip/sys/d21x/boot_param.c
View File

@@ -1,5 +1,8 @@
/*
* Copyright (C) 2023 ArtInChip Technology Co.,Ltd
* Copyright (C) 2023-2024 ArtInChip Technology Co.,Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
* Author: Dehuang Wu <dehuang.wu@artinchip.com>
*/
@@ -11,6 +14,7 @@
* Save boot parameters and context when save_boot_params is called.
*/
union boot_params boot_params_stash __attribute__((section(".data")));
struct boot_args boot_arg __attribute__((section(".data")));
enum boot_reason aic_get_boot_reason(void)
{
@@ -77,3 +81,8 @@ unsigned long aic_timer_get_us(void)
return (tick >> 2);
}
void *aic_get_boot_args(void)
{
return (void *)&boot_arg;
}

25
bsp/artinchip/sys/d21x/boot_param_gcc.S
View File

@@ -1,8 +1,11 @@
/*
* Copyright (C) 2020 ArtInChip Technology Co.,Ltd
* Copyright (C) 2023-2024 ArtInChip Technology Co.,Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
* Author: Dehuang Wu <dehuang.wu@artinchip.com>
*/
#include <rtconfig.h>
#define LREG ld
#define SREG sd
#define REGBYTES 8
@@ -11,6 +14,9 @@
#define SYM_SIZE 0x18
.extern boot_params_stash
#ifndef AIC_BOOTLOADER
.extern boot_arg
#endif
.global save_boot_params
.type save_boot_params, %function
@@ -38,5 +44,20 @@ save_boot_params:
SREG s11, REGBYTES * 19(t0)
SREG sp, REGBYTES * 20(t0)
SREG ra, REGBYTES * 21(t0)
#ifndef AIC_BOOTLOADER
beqz a1, 2f
/* copy boot_arg from SPL to OS */
la t0, boot_arg
mv t1, a1
/* boot_arg size is 256 bytes */
addi t2, t1, 0xFF
1:
LREG t3, (t1)
SREG t3, (t0)
addi t0, t0, REGBYTES
addi t1, t1, REGBYTES
bltu t1, t2, 1b
2:
#endif
j save_boot_params_ret

8
bsp/artinchip/sys/d21x/include/aic_drv_irq.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022, Artinchip Technology Co., Ltd
* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -13,6 +13,12 @@ extern "C" {
#include <stdint.h>
#ifdef AIC_GPIO_IRQ_DRV_EN
#define MAX_IRQ_ENTRY (MAX_IRQn+GPIO_MAX_PIN)
#else
#define MAX_IRQ_ENTRY (MAX_IRQn)
#endif
#define AIC_GPIO_TO_IRQ(GPIOn)(MAX_IRQn + (GPIOn))
#define AIC_IRQ_TO_GPIO(IRQn)((IRQn) - MAX_IRQn)

11
bsp/artinchip/sys/d21x/include/boot_param.h
View File

@@ -1,5 +1,8 @@
/*
* Copyright (C) 2023 ArtInChip Technology Co.,Ltd
* Copyright (C) 2023-2024 ArtInChip Technology Co.,Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
* Author: Dehuang Wu <dehuang.wu@artinchip.com>
*/
#ifndef __BOOT_PARAM_H__
@@ -67,6 +70,11 @@ enum boot_controller {
BC_USB,
};
struct boot_args {
char image_version[16];
char reserved[240];
};
#define BD_BOOTROM BD_USB
typedef int (*nand_read)(void *dev, unsigned long offset, void *buf,
@@ -79,4 +87,5 @@ unsigned long aic_timer_get_us(void);
void *aic_get_boot_resource(void);
void *aic_get_boot_resource_from_nand(void *dev, unsigned long pagesize,
nand_read fn);
void *aic_get_boot_args(void);
#endif /* __BOOT_PARAM_H__ */

9
bsp/artinchip/sys/d21x/include/core_rv64.h
View File

@@ -1005,9 +1005,8 @@ __STATIC_INLINE void csi_dcache_invalid_range(phy_addr_t addr, u32 dsize)
asm volatile (".long 0x02a7800b"); /* dcache.ipa a5 */
#endif
__DSB();
__ISB();
__SYNC_IS();
__DSB();
#endif
}
@@ -1048,9 +1047,8 @@ __STATIC_INLINE void csi_dcache_clean_range(phy_addr_t addr, u32 dsize)
asm volatile (".long 0x0297800b"); /* dcache.cpa a5 */
#endif
__DSB();
__ISB();
__SYNC_IS();
__DSB();
#endif
}
@@ -1091,9 +1089,8 @@ __STATIC_INLINE void csi_dcache_clean_invalid_range(phy_addr_t addr, u32 dsize)
asm volatile (".long 0x02b7800b"); /* dcache.cipa a5 */
#endif
__DSB();
__ISB();
__SYNC_IS();
__DSB();
#endif
}

10
bsp/artinchip/sys/d21x/include/csi_rv64_gcc.h
View File

@@ -1346,6 +1346,7 @@ __ALWAYS_STATIC_INLINE void __STOP(void)
__ALWAYS_STATIC_INLINE void __ISB(void)
{
__ASM volatile("fence.i");
__ASM volatile("fence r, r");
}
@@ -1356,7 +1357,12 @@ __ALWAYS_STATIC_INLINE void __ISB(void)
*/
__ALWAYS_STATIC_INLINE void __DSB(void)
{
__ASM volatile("fence");
__ASM volatile("fence iorw, iorw");
#ifdef __riscv_xthead
__ASM volatile("sync");
#else
asm volatile (".long 0x0180000b"); /* sync */
#endif
}
/**
@@ -1616,7 +1622,7 @@ __ALWAYS_STATIC_INLINE void __DCACHE_CIVA(uint64_t addr)
*/
__ALWAYS_STATIC_INLINE void __DMB(void)
{
__ASM volatile("fence");
__ASM volatile("fence rw, rw");
}
/**

1
bsp/artinchip/sys/d21x/link_script/gcc_aic.ld.S
View File

@@ -49,6 +49,7 @@ PROVIDE (__dram_sw_start = __dram_start);
PROVIDE (__dram_sw_end = __dram_end - AIC_DRAM_CMA_SIZE);
PROVIDE (__dram_cma_start = __dram_sw_end);
PROVIDE (__dram_cma_end = __dram_end);
PROVIDE (__dtb_pos_f = __dram_end - 0x40000);
PROVIDE (__dram_cma_heap_end = __dram_cma_end);
PROVIDE (__dram_sw_heap_end = __dram_sw_end);