v1.0.3

bsp/artinchip/drv/display/Kconfig

@@ -26,24 +26,28 @@ config AIC_DISP_MIPI_DSI_DRV
 
 choice
     prompt "select Display interface"
-    default AIC_DISP_LVDS
+    default AIC_DISP_RGB
     depends on AIC_DISPLAY_DRV
 
 config AIC_DISP_RGB
     bool "Display RGB interface"
     select AIC_DISP_RGB_DRV
+    depends on AIC_DE_DRV_V10 || AIC_DE_DRV_V11 || AIC_DE_DRV_V12
 
 config AIC_DISP_LVDS
     bool "Display LVDS interface"
     select AIC_DISP_LVDS_DRV
+    depends on AIC_DE_DRV_V10 || AIC_DE_DRV_V11
 
 config AIC_DISP_MIPI_DSI
     bool "Display MIPI-DSI interface"
     select AIC_DISP_MIPI_DSI_DRV
+    depends on AIC_DE_DRV_V10 || AIC_DE_DRV_V11
 
 config AIC_DISP_MIPI_DBI
     bool "Display MIPI-DBI interface"
     select AIC_DISP_MIPI_DBI_DRV
+    depends on AIC_DE_DRV_V10 || AIC_DE_DRV_V11 || AIC_DE_DRV_V12
 endchoice
 
 config AIC_DI_TYPE
@@ -194,3 +198,7 @@ if AIC_PWM_BACKLIGHT
         default 80
         range 0 100
 endif
+
+config AIC_PANEL_SPI_EMULATION
+    bool
+    default n

bsp/artinchip/drv/display/Kconfig.lvds

@@ -34,6 +34,7 @@ choice
 
 config AIC_LVDS_LINK_0
     bool "single link 0"
+    depends on AIC_DE_DRV_V10 || AIC_DE_DRV_V11
 
 config AIC_LVDS_LINK_1
     bool "single link 1"
@@ -41,9 +42,11 @@ config AIC_LVDS_LINK_1
 
 config AIC_LVDS_DOUBLE_SCREEN
     bool "double screen"
+    depends on AIC_DE_DRV_V10
 
 config AIC_LVDS_DUAL_LINK
     bool "dual link"
+    depends on AIC_DE_DRV_V10
 endchoice
 
 config AIC_LVDS_LINK_MODE

bsp/artinchip/drv/display/disp_com.h

@@ -129,6 +129,7 @@ struct di_funcs {
     int (*attach_panel)(struct aic_panel *panel);
     int (*set_videomode)(const struct display_timing *timings, int enable);
     int (*send_cmd)(u32 dt, u32 vc, const u8 *data, u32 len);
+    int (*read_cmd)(u32 val);
 };
 
 struct platform_driver {

bsp/artinchip/drv/display/disp_conf.h

@@ -42,16 +42,23 @@
  */
 
 /* data line assignments */
-#define LANE_ASSIGNMENTS 0x0123;
+#define LANE_ASSIGNMENTS 0x3210;
 
 /* data line polarities */
-#define LANE_POLARITIES  0b1111;
+#define LANE_POLARITIES  0b0000;
 
 /* data clk inverse */
-#define CLK_INVERSE      1
+#define CLK_INVERSE      0
 
+/* virtual channel id */
 #define VIRTUAL_CHANNEL  0
 
+/* mipi-dsi lp rate, range [10M, 20M], default 10M */
+#define MIPI_DSI_LP_RATE    (10 * 1000 * 1000)
+
+/* mipi-dsi dcs get display id from screen when panel enable */
+#define DCS_GET_DISPLAY_ID  0
+
 /**
  * FB ROTATION options
  */

bsp/artinchip/drv/display/drv_de.c

@@ -86,6 +86,12 @@ static irqreturn_t aic_de_handler(int irq, void *ctx)
 
 static inline bool is_valid_layer_id(struct aic_de_comp *comp, u32 layer_id)
 {
+#if defined(AIC_DE_DRV_V12) || defined(AIC_DE_V12)
+    if (layer_id != AICFB_LAYER_TYPE_UI)
+        return false;
+    else
+        return true;
+#else
     u32 total_num = comp->config->layer_num->vi_num
             + comp->config->layer_num->ui_num;
 
@@ -93,6 +99,7 @@ static inline bool is_valid_layer_id(struct aic_de_comp *comp, u32 layer_id)
         return true;
     else
         return false;
+#endif
 }
 
 static inline bool need_update_disp_prop(struct aic_de_comp *comp,
@@ -193,6 +200,12 @@ static int aic_de_set_mode(struct aic_panel *panel)
 
     comp->timing = panel->timings;
 
+#ifdef AIC_DISPLAY_DITHER
+    if (comp->timing->hactive > DE_DITHER_WIDTH_MAX) {
+        memset(&comp->dither, 0x00, sizeof(struct aic_de_dither));
+        pr_err("Screen width is invalid, disable dither\n");
+    }
+#endif
     return 0;
 }
 
@@ -1326,14 +1339,14 @@ struct de_funcs aic_de_funcs = {
 };
 
 static const struct aicfb_layer_num layer_num = {
-    .vi_num = 1,
-    .ui_num = 1,
+    .vi_num = VI_LAYER_NUM,
+    .ui_num = UI_LAYER_NUM,
 };
 
 static const struct aicfb_layer_capability aicfb_layer_cap[] = {
-    {0, AICFB_LAYER_TYPE_VIDEO, 2048, 2048, AICFB_CAP_SCALING_FLAG},
-    {1, AICFB_LAYER_TYPE_UI, 2048, 2048,
-    AICFB_CAP_4_RECT_WIN_FLAG|AICFB_CAP_ALPHA_FLAG|AICFB_CAP_CK_FLAG},
+    {0, AICFB_LAYER_TYPE_VIDEO, VI_LAYER_WIDTH_MAX, VI_LAYER_HEIGHT_MAX, 0},
+    {1, AICFB_LAYER_TYPE_UI,    UI_LAYER_WIDTH_MAX, UI_LAYER_HEIGHT_MAX,
+     AICFB_CAP_4_RECT_WIN_FLAG | AICFB_CAP_ALPHA_FLAG | AICFB_CAP_CK_FLAG},
 };
 
 static const struct aic_de_configs aic_de_cfg = {

bsp/artinchip/drv/display/drv_dsi.c

@@ -7,6 +7,7 @@
 #include <aic_core.h>
 #include <aic_hal.h>
 #include <aic_hal_dsi.h>
+#include <mipi_display.h>
 
 #include "disp_com.h"
 
@@ -67,6 +68,7 @@ static int aic_dsi_enable(void)
 {
     struct aic_dsi_comp *comp = aic_dsi_request_drvdata();
     struct panel_dsi *dsi = comp->panel->dsi;
+    ulong lp_rate = MIPI_DSI_LP_RATE;
 
     reg_set_bit(comp->regs + DSI_CTL, DSI_CTL_EN);
 
@@ -74,7 +76,12 @@ static int aic_dsi_enable(void)
     dsi_set_lane_polrs(comp->regs, comp->ln_polrs);
     dsi_set_data_clk_polrs(comp->regs, comp->dc_inv);
 
-    dsi_set_clk_div(comp->regs, comp->sclk_rate);
+    if (lp_rate < 10000000 || lp_rate > 20000000) {
+        lp_rate = 10000000;
+        pr_warn("Invalid lp rate, use default lp rate: %ld\n", lp_rate);
+    }
+
+    dsi_set_clk_div(comp->regs, comp->sclk_rate, lp_rate);
     dsi_pkg_init(comp->regs);
     dsi_phy_init(comp->regs, comp->sclk_rate, dsi->lane_num);
     dsi_hs_clk(comp->regs, 1);
@@ -138,6 +145,13 @@ static int aic_dsi_set_vm(const struct display_timing *timing, int enable)
         dsi_set_vm(comp->regs, DSI_MOD_CMD_MODE, dsi->format,
             dsi->lane_num, comp->vc_num, timing);
         dsi_dcs_lw(comp->regs, true);
+#if DCS_GET_DISPLAY_ID
+        dsi_cmd_wr(comp->regs, MIPI_DSI_DCS_READ, 0,
+                (u8[]){ MIPI_DCS_GET_DISPLAY_ID }, 1);
+        aic_delay_ms(120);
+
+        pr_info("mipi-dsi screen id: %x\n", readl(comp->regs + DSI_GEN_PD_CFG));
+#endif
     }
 
     aic_dsi_release_drvdata();
@@ -153,6 +167,16 @@ static int aic_dsi_send_cmd(u32 dt, u32 vc, const u8 *data, u32 len)
     return 0;
 }
 
+static int aic_dsi_read_cmd(u32 val)
+{
+    struct aic_dsi_comp *comp = aic_dsi_request_drvdata();
+
+    dsi_cmd_wr(comp->regs, MIPI_DSI_DCS_READ, 0, (u8[]){ val }, 1);
+    aic_delay_ms(120);
+
+    return readl(comp->regs + DSI_GEN_PD_CFG);
+}
+
 struct di_funcs aic_dsi_func = {
     .clk_enable = aic_dsi_clk_enable,
     .clk_disable = aic_dsi_clk_disable,
@@ -161,6 +185,7 @@ struct di_funcs aic_dsi_func = {
     .attach_panel = aic_dsi_attach_panel,
     .set_videomode = aic_dsi_set_vm,
     .send_cmd = aic_dsi_send_cmd,
+    .read_cmd = aic_dsi_read_cmd,
 };
 
 static int aic_dsi_probe(void)

bsp/artinchip/drv/display/drv_fb.c

@@ -161,6 +161,15 @@ int aicfb_ioctl(int cmd, void *args)
     case AICFB_WAIT_FOR_VSYNC:
         return fbi->de->de_funcs->wait_for_vsync();
 
+    case AICFB_GET_SCREENREG:
+    {
+        if (!fbi->di->di_funcs->read_cmd) {
+            pr_err("display interface do not supports AICFB_GET_SCREENREG\n");
+            return -EINVAL;
+        }
+
+        return fbi->di->di_funcs->read_cmd(*(u32 *)args);
+    }
     case AICFB_GET_SCREENINFO:
     {
         const struct display_timing *timing = fbi->panel->timings;
@@ -386,7 +395,7 @@ rt_err_t aicfb_control(rt_device_t dev, int cmd, void *args)
 }
 
 #ifdef RT_USING_DEVICE_OPS
-const static struct rt_device_ops aicfb_ops =
+static const struct rt_device_ops aicfb_ops =
 {
     RT_NULL,
     RT_NULL,
@@ -635,6 +644,14 @@ static void fb_color_block(struct aicfb_info *fbi)
         break;
     }
 #endif
+    default:
+        *pos = color[0][0];
+        index = AICFB_FORMAT;
+        i = width;
+        j = height;
+
+        pr_info("format(%d) do not support %dx%d color block.\n", index, i, j);
+        return;
     }
 
     aicos_dcache_clean_range((unsigned long *)fbi->fb_start, fbi->fb_size);

bsp/artinchip/drv/display/drv_rgb.c

@@ -100,6 +100,7 @@ static int aic_rgb_enable(void)
             reg_set_bit(comp->regs + RGB_LCD_CTL,
                     RGB_LCD_CTL_SRGB_MODE);
         aic_rgb_swap();
+        break;
     default:
         pr_err("Invalid mode %d\n", rgb->mode);
         break;
@@ -140,7 +141,7 @@ static int aic_rgb_attach_panel(struct aic_panel *panel)
 #ifdef AIC_DISP_RGB_DRV_V10
         comp->sclk_rate = pixclk * 12;
 #else
-        comp->sclk_rate = pixclk * 16;
+        comp->sclk_rate = pixclk * 6;
 #endif
 
     pll_disp_rate = comp->sclk_rate;

bsp/artinchip/drv/display/panel/Kconfig

@@ -33,6 +33,11 @@ menu "Display Panels"
         bool "ArtInChip MIPI DBI ili9486l panel"
         depends on AIC_DISP_MIPI_DBI
 
+    config AIC_PANEL_RGB_ST7701S
+        bool "ArtInChip rgb st7701s panel"
+        depends on AIC_DISP_RGB
+        select AIC_PANEL_SPI_EMULATION
+
     config AIC_PANEL_SRGB_HX8238
         bool "ArtInChip srgb hx8238 panel"
         depends on AIC_DISP_RGB

bsp/artinchip/drv/display/panel/panel_com.c

@@ -35,6 +35,9 @@ static struct aic_panel *panels[] = {
 #ifdef AIC_PANEL_DBI_ILI9486L
     &dbi_ili9486l,
 #endif
+#ifdef AIC_PANEL_RGB_ST7701S
+    &rgb_st7701s,
+#endif
 #ifdef AIC_PANEL_SRGB_HX8238
     &srgb_hx8238
 #endif
@@ -230,3 +233,111 @@ void panel_gpio_set_value(struct gpio_desc *desc, u32 value)
     else
         hal_gpio_clr_output(desc->g, desc->p);
 }
+
+#ifdef AIC_PANEL_SPI_EMULATION
+static struct panel_spi_device spi = { 0 };
+static bool panel_spi_emulation = false;
+
+static inline void panel_spi_set_scl(u32 value)
+{
+    panel_gpio_set_value(&spi.scl, value);
+}
+
+static inline void panel_spi_set_sdi(u32 value)
+{
+    panel_gpio_set_value(&spi.sdi, value);
+}
+
+static inline void panel_spi_set_cs(u32 value)
+{
+    panel_gpio_set_value(&spi.cs, value);
+}
+
+void panel_spi_cmd_wr(u8 cmd)
+{
+    u32 i;
+
+    if (!panel_spi_emulation)
+        return;
+
+    panel_spi_set_cs(0);
+
+    panel_spi_set_sdi(0);
+    panel_spi_set_scl(0);
+
+    aic_delay_us(1);
+    panel_spi_set_scl(1);
+
+    aic_delay_us(1);
+    panel_spi_set_scl(0);
+
+    for (i = 0; i < 8; i++) {
+        if ((cmd & 0x80) == 0x80)
+            panel_spi_set_sdi(1);
+        else
+            panel_spi_set_sdi(0);
+
+        aic_delay_us(1);
+        panel_spi_set_scl(1);
+        aic_delay_us(1);
+        panel_spi_set_scl(0);
+        aic_delay_us(1);
+        cmd = cmd << 1;
+    }
+
+    panel_spi_set_cs(1);
+    panel_spi_set_sdi(0);
+    panel_spi_set_scl(0);
+    aic_delay_us(1);
+}
+
+void panel_spi_data_wr(u8 data)
+{
+    u32 i;
+
+    if (!panel_spi_emulation)
+        return;
+
+    panel_spi_set_cs(0);
+    panel_spi_set_scl(0);
+    panel_spi_set_sdi(1);
+
+    aic_delay_us(1);
+    panel_spi_set_scl(1);
+
+    aic_delay_us(1);
+    panel_spi_set_scl(0);
+
+    for (i = 0; i < 8; i++) {
+        if ((data & 0x80) == 0x80)
+            panel_spi_set_sdi(1);
+        else
+            panel_spi_set_sdi(0);
+
+        aic_delay_us(1);
+        panel_spi_set_scl(1);
+        aic_delay_us(1);
+        panel_spi_set_scl(0);
+        aic_delay_us(1);
+        data = data << 1;
+    }
+    panel_spi_set_cs(1);
+    panel_spi_set_scl(0);
+    panel_spi_set_sdi(0);
+    aic_delay_us(1);
+}
+
+void panel_spi_device_emulation(char *cs, char *sdi, char *scl)
+{
+    panel_get_gpio(&spi.cs, cs);
+    panel_get_gpio(&spi.scl, scl);
+    panel_get_gpio(&spi.sdi, sdi);
+
+    panel_spi_set_cs(1);
+    panel_spi_set_scl(0);
+    panel_spi_set_sdi(0);
+    aic_delay_us(1);
+
+    panel_spi_emulation = true;
+}
+#endif

bsp/artinchip/drv/display/panel/panel_com.h

@@ -27,6 +27,7 @@ extern struct aic_panel dbi_ili9341;
 extern struct aic_panel dbi_st77903;
 extern struct aic_panel dbi_ili9486l;
 extern struct aic_panel srgb_hx8238;
+extern struct aic_panel rgb_st7701s;
 
 void panel_di_enable(struct aic_panel *panel, u32 ms);
 void panel_di_disable(struct aic_panel *panel, u32 ms);
@@ -50,5 +51,17 @@ void panel_get_gpio(struct gpio_desc *desc, char *name);
 
 void panel_gpio_set_value(struct gpio_desc *desc, u32 value);
 
+#ifdef AIC_PANEL_SPI_EMULATION
+struct panel_spi_device {
+    struct gpio_desc cs;
+    struct gpio_desc sdi;
+    struct gpio_desc scl;
+};
+
+void panel_spi_data_wr(u8 data);
+void panel_spi_cmd_wr(u8 cmd);
+void panel_spi_device_emulation(char *cs, char *sdi, char *scl);
+#endif
+
 #endif /* _PANEL_COM_H_ */
 

bsp/artinchip/drv/display/panel/panel_dbi_ili9341.c

@@ -66,7 +66,7 @@ static struct aic_panel_funcs ili9341_funcs = {
 };
 
 static struct display_timing ili9341_timing = {
-    .pixelclock   = 12000000,
+    .pixelclock   = 3000000,
 
     .hactive      = 240,
     .hback_porch  = 2,

bsp/artinchip/drv/display/panel/panel_rgb_st7701s.c

@@ -0,0 +1,357 @@
+/*
+ * Copyright (c) 2023, Artinchip Technology Co., Ltd
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "panel_com.h"
+#include <aic_hal.h>
+
+#define SLEEP_PIN  "PE.1"
+#define RESET_PIN  "PE.2"
+
+#define CS         "PE.3"
+#define SCL        "PA.8"
+#define SDI        "PA.9"
+
+static struct gpio_desc reset_gpio;
+static struct gpio_desc sleep_gpio;
+
+static void panel_gpio_init(void)
+{
+    panel_get_gpio(&reset_gpio, RESET_PIN);
+    panel_get_gpio(&sleep_gpio, SLEEP_PIN);
+
+    panel_gpio_set_value(&sleep_gpio, 1);
+    aic_delay_ms(2);
+    panel_gpio_set_value(&reset_gpio, 0);
+    aic_delay_ms(20);
+    panel_gpio_set_value(&reset_gpio, 1);
+    aic_delay_ms(120);
+}
+
+static int panel_enable(struct aic_panel *panel)
+{
+    panel_gpio_init();
+
+    panel_spi_device_emulation(CS, SDI, SCL);
+
+    panel_spi_cmd_wr(0xFF);
+    panel_spi_data_wr(0x77);
+    panel_spi_data_wr(0x01);
+    panel_spi_data_wr(0x00);
+    panel_spi_data_wr(0x00);
+    panel_spi_data_wr(0x13);
+    panel_spi_cmd_wr(0xEF);
+    panel_spi_data_wr(0x08);
+    panel_spi_cmd_wr(0xFF);
+    panel_spi_data_wr(0x77);
+    panel_spi_data_wr(0x01);
+    panel_spi_data_wr(0x00);
+    panel_spi_data_wr(0x00);
+    panel_spi_data_wr(0x10);
+    panel_spi_cmd_wr(0xC0);
+    panel_spi_data_wr(0x77);
+    panel_spi_data_wr(0x00);
+    panel_spi_cmd_wr(0xC1);
+    panel_spi_data_wr(0x0E);
+    panel_spi_data_wr(0x0C);
+    panel_spi_cmd_wr(0xC2);
+    panel_spi_data_wr(0x07);
+    panel_spi_data_wr(0x02);
+
+    panel_spi_cmd_wr(0xC3);
+    panel_spi_data_wr(0x00);
+
+    panel_spi_cmd_wr(0xCC);
+    panel_spi_data_wr(0x30);
+
+    panel_spi_cmd_wr(0xCD);
+    panel_spi_data_wr(0x08);
+
+    panel_spi_cmd_wr(0xB0);
+    panel_spi_data_wr(0x00);
+    panel_spi_data_wr(0x17);
+    panel_spi_data_wr(0x1F);
+    panel_spi_data_wr(0x0E);
+    panel_spi_data_wr(0x11);
+    panel_spi_data_wr(0x06);
+    panel_spi_data_wr(0x0D);
+    panel_spi_data_wr(0x08);
+    panel_spi_data_wr(0x07);
+    panel_spi_data_wr(0x26);
+    panel_spi_data_wr(0x03);
+    panel_spi_data_wr(0x11);
+    panel_spi_data_wr(0x0F);
+    panel_spi_data_wr(0x2A);
+    panel_spi_data_wr(0x31);
+    panel_spi_data_wr(0x1C);
+    panel_spi_cmd_wr(0xB1);
+    panel_spi_data_wr(0x00);
+    panel_spi_data_wr(0x17);
+    panel_spi_data_wr(0x1F);
+    panel_spi_data_wr(0x0D);
+    panel_spi_data_wr(0x11);
+    panel_spi_data_wr(0x07);
+    panel_spi_data_wr(0x0C);
+    panel_spi_data_wr(0x08);
+    panel_spi_data_wr(0x08);
+    panel_spi_data_wr(0x26);
+    panel_spi_data_wr(0x04);
+    panel_spi_data_wr(0x11);
+    panel_spi_data_wr(0x0F);
+    panel_spi_data_wr(0x2A);
+    panel_spi_data_wr(0x31);
+    panel_spi_data_wr(0x1C);
+    panel_spi_cmd_wr(0xFF);
+    panel_spi_data_wr(0x77);
+    panel_spi_data_wr(0x01);
+    panel_spi_data_wr(0x00);
+    panel_spi_data_wr(0x00);
+    panel_spi_data_wr(0x11);
+    panel_spi_cmd_wr(0xB0);
+    panel_spi_data_wr(0x5C);
+    panel_spi_cmd_wr(0xB1);
+    panel_spi_data_wr(0x60);
+    panel_spi_cmd_wr(0xB2);
+    panel_spi_data_wr(0x85);
+    panel_spi_cmd_wr(0xB3);
+    panel_spi_data_wr(0x80);
+    panel_spi_cmd_wr(0xB5);
+    panel_spi_data_wr(0x49);
+    panel_spi_cmd_wr(0xB7);
+    panel_spi_data_wr(0x87);
+    panel_spi_cmd_wr(0xB8);
+    panel_spi_data_wr(0x22);
+
+    panel_spi_cmd_wr(0xC0);
+    panel_spi_data_wr(0x09);
+    panel_spi_cmd_wr(0xC1);
+    panel_spi_data_wr(0x88);
+    panel_spi_cmd_wr(0xC2);
+    panel_spi_data_wr(0x88);
+    panel_spi_cmd_wr(0xD0);
+    panel_spi_data_wr(0x88);
+    panel_spi_cmd_wr(0xE0);
+    panel_spi_data_wr(0x00);
+    panel_spi_data_wr(0x00);
+    panel_spi_data_wr(0x02);
+    panel_spi_data_wr(0x00);
+    panel_spi_data_wr(0x00);
+    panel_spi_data_wr(0x0C);
+    panel_spi_cmd_wr(0xE1);
+    panel_spi_data_wr(0x03);
+    panel_spi_data_wr(0x96);
+    panel_spi_data_wr(0x05);
+    panel_spi_data_wr(0x96);
+    panel_spi_data_wr(0x02);
+    panel_spi_data_wr(0x96);
+    panel_spi_data_wr(0x04);
+    panel_spi_data_wr(0x96);
+    panel_spi_data_wr(0x00);
+    panel_spi_data_wr(0x44);
+    panel_spi_data_wr(0x44);
+    panel_spi_cmd_wr(0xE2);
+    panel_spi_data_wr(0x00);
+    panel_spi_data_wr(0x00);
+    panel_spi_data_wr(0x03);
+    panel_spi_data_wr(0x03);
+    panel_spi_data_wr(0x00);
+    panel_spi_data_wr(0x00);
+    panel_spi_data_wr(0x02);
+    panel_spi_data_wr(0x00);
+    panel_spi_data_wr(0x00);
+    panel_spi_data_wr(0x00);
+    panel_spi_data_wr(0x02);
+    panel_spi_data_wr(0x00);
+    panel_spi_cmd_wr(0xE3);
+    panel_spi_data_wr(0x00);
+    panel_spi_data_wr(0x00);
+    panel_spi_data_wr(0x33);
+    panel_spi_data_wr(0x33);
+    panel_spi_cmd_wr(0xE4);
+    panel_spi_data_wr(0x44);
+    panel_spi_data_wr(0x44);
+    panel_spi_cmd_wr(0xE5);
+    panel_spi_data_wr(0x0B);
+    panel_spi_data_wr(0xD4);
+    panel_spi_data_wr(0x28);
+    panel_spi_data_wr(0x8C);
+    panel_spi_data_wr(0x0D);
+    panel_spi_data_wr(0xD6);
+    panel_spi_data_wr(0x28);
+    panel_spi_data_wr(0x8C);
+    panel_spi_data_wr(0x07);
+    panel_spi_data_wr(0xD0);
+    panel_spi_data_wr(0x28);
+    panel_spi_data_wr(0x8C);
+    panel_spi_data_wr(0x09);
+    panel_spi_data_wr(0xD2);
+    panel_spi_data_wr(0x28);
+    panel_spi_data_wr(0x8C);
+    panel_spi_cmd_wr(0xE6);
+    panel_spi_data_wr(0x00);
+    panel_spi_data_wr(0x00);
+    panel_spi_data_wr(0x33);
+    panel_spi_data_wr(0x33);
+    panel_spi_cmd_wr(0xE7);
+    panel_spi_data_wr(0x44);
+    panel_spi_data_wr(0x44);
+    panel_spi_cmd_wr(0xE8);
+    panel_spi_data_wr(0x0A);
+    panel_spi_data_wr(0xD5);
+    panel_spi_data_wr(0x28);
+    panel_spi_data_wr(0x8C);
+    panel_spi_data_wr(0x0C);
+    panel_spi_data_wr(0xD7);
+    panel_spi_data_wr(0x28);
+    panel_spi_data_wr(0x8C);
+    panel_spi_data_wr(0x06);
+    panel_spi_data_wr(0xD1);
+    panel_spi_data_wr(0x28);
+    panel_spi_data_wr(0x8C);
+    panel_spi_data_wr(0x08);
+    panel_spi_data_wr(0xD3);
+    panel_spi_data_wr(0x28);
+    panel_spi_data_wr(0x8C);
+    panel_spi_cmd_wr(0xEB);
+    panel_spi_data_wr(0x00);
+    panel_spi_data_wr(0x01);
+    panel_spi_data_wr(0xE4);
+    panel_spi_data_wr(0xE4);
+    panel_spi_data_wr(0x44);
+    panel_spi_data_wr(0x00);
+    panel_spi_cmd_wr(0xED);
+    panel_spi_data_wr(0xFF);
+    panel_spi_data_wr(0x45);
+    panel_spi_data_wr(0x67);
+    panel_spi_data_wr(0xFC);
+    panel_spi_data_wr(0x01);
+    panel_spi_data_wr(0x3F);
+    panel_spi_data_wr(0xAB);
+    panel_spi_data_wr(0xFF);
+    panel_spi_data_wr(0xFF);
+    panel_spi_data_wr(0xBA);
+    panel_spi_data_wr(0xF3);
+    panel_spi_data_wr(0x10);
+    panel_spi_data_wr(0xCF);
+    panel_spi_data_wr(0x76);
+    panel_spi_data_wr(0x54);
+    panel_spi_data_wr(0xFF);
+    panel_spi_cmd_wr(0xEF);
+    panel_spi_data_wr(0x08);
+    panel_spi_data_wr(0x08);
+    panel_spi_data_wr(0x08);
+    panel_spi_data_wr(0x45);
+    panel_spi_data_wr(0x3F);
+    panel_spi_data_wr(0x54);
+    panel_spi_cmd_wr(0xFF);
+    panel_spi_data_wr(0x77);
+    panel_spi_data_wr(0x01);
+    panel_spi_data_wr(0x00);
+    panel_spi_data_wr(0x00);
+    panel_spi_data_wr(0x13);
+    panel_spi_cmd_wr(0xE8);
+    panel_spi_data_wr(0x00);
+    panel_spi_data_wr(0x0E);
+
+    panel_spi_cmd_wr(0xE8);
+    panel_spi_data_wr(0x00);
+    panel_spi_data_wr(0x0C);
+
+    aic_delay_ms(20);
+
+    panel_spi_cmd_wr(0xE8);
+    panel_spi_data_wr(0x40);
+    panel_spi_data_wr(0x00);
+    panel_spi_cmd_wr(0xE6);
+    panel_spi_data_wr(0x16);
+    panel_spi_data_wr(0x7C);
+    panel_spi_cmd_wr(0xFF);
+    panel_spi_data_wr(0x77);
+    panel_spi_data_wr(0x01);
+    panel_spi_data_wr(0x00);
+    panel_spi_data_wr(0x00);
+    panel_spi_data_wr(0x00);
+    panel_spi_cmd_wr(0x36);
+    panel_spi_data_wr(0x00);
+    panel_spi_cmd_wr(0x35);
+    panel_spi_data_wr(0x00);
+
+    panel_spi_cmd_wr(0x3a);
+    panel_spi_data_wr(0x66);
+
+#ifdef BIST_MODE
+    panel_spi_cmd_wr (0xFF);
+    panel_spi_data_wr (0x77);
+    panel_spi_data_wr (0x01);
+    panel_spi_data_wr (0x00);
+    panel_spi_data_wr (0x00);
+    panel_spi_data_wr (0x12);
+    panel_spi_cmd_wr (0xD1);
+    panel_spi_data_wr (0x81);
+    panel_spi_data_wr (0x08);
+    panel_spi_data_wr (0x03);
+    panel_spi_data_wr (0x20);
+    panel_spi_data_wr (0x08);
+    panel_spi_data_wr (0x01);
+    panel_spi_data_wr (0xA0);
+    panel_spi_data_wr (0x01);
+    panel_spi_data_wr (0xE0);
+    panel_spi_data_wr (0xA0);
+    panel_spi_data_wr (0x01);
+    panel_spi_data_wr (0xE0);
+    panel_spi_data_wr (0x03);
+    panel_spi_data_wr (0x20);
+    panel_spi_cmd_wr (0xD2);
+    /* 0x08: colorbar, 0X02: red  etc... */
+    panel_spi_data_wr (0x08);
+#endif
+
+    panel_spi_cmd_wr(0x11);
+    aic_delay_ms(120);
+    panel_spi_cmd_wr(0x29);
+    aic_delay_ms(120);
+
+    panel_di_enable(panel, 0);
+    panel_de_timing_enable(panel, 0);
+    panel_backlight_enable(panel, 0);
+    return 0;
+}
+
+static struct aic_panel_funcs st7701s_funcs = {
+    .disable = panel_default_disable,
+    .unprepare = panel_default_unprepare,
+    .prepare = panel_default_prepare,
+    .enable = panel_enable,
+    .register_callback = panel_register_callback,
+};
+
+static struct display_timing st7701s_timing = {
+    .pixelclock = 42000000,
+    .hactive = 400,
+    .hfront_porch = 100,
+    .hback_porch = 100,
+    .hsync_len = 10,
+    .vactive = 960,
+    .vfront_porch = 80,
+    .vback_porch = 100,
+    .vsync_len = 20,
+};
+
+static struct panel_rgb rgb = {
+    .mode = PRGB,
+    .format = PRGB_24BIT,
+    .clock_phase = DEGREE_0,
+    .data_order = RGB,
+    .data_mirror = 0,
+};
+
+struct aic_panel rgb_st7701s = {
+    .name = "panel-st7701s",
+    .timings = &st7701s_timing,
+    .funcs = &st7701s_funcs,
+    .rgb = &rgb,
+    .connector_type = AIC_RGB_COM,
+};
+

bsp/artinchip/drv/display/panel/panel_srgb_hx8238.c

@@ -16,7 +16,7 @@ static struct gpio_desc scl;
 static struct gpio_desc cs;
 static struct gpio_desc reset;
 
-static void HX8238_send_cmd(unsigned char cmd)
+static void hx8238_send_cmd(unsigned char cmd)
 {
     int i;
 
@@ -36,7 +36,7 @@ static void HX8238_send_cmd(unsigned char cmd)
     }
 }
 
-static void HX8238_send_data(unsigned int data)
+static void hx8238_send_data(unsigned int data)
 {
     int i;
 
@@ -56,7 +56,7 @@ static void HX8238_send_data(unsigned int data)
     }
 }
 
-static void HX8238_write(unsigned char code,unsigned int data)
+static void hx8238_write(unsigned char code,unsigned int data)
 {
     panel_gpio_set_value(&sda, 1);
     panel_gpio_set_value(&scl, 1);
@@ -66,8 +66,8 @@ static void HX8238_write(unsigned char code,unsigned int data)
     panel_gpio_set_value(&cs, 0);
     aic_delay_us(50);
 
-    HX8238_send_cmd(code);
-    HX8238_send_data(data);
+    hx8238_send_cmd(code);
+    hx8238_send_data(data);
 
     panel_gpio_set_value(&scl, 0);
     aic_delay_us(5);
@@ -77,7 +77,7 @@ static void HX8238_write(unsigned char code,unsigned int data)
     panel_gpio_set_value(&cs, 1);
 }
 
-void HX8238_init(void)
+void hx8238_init(void)
 {
     panel_get_gpio(&sda, SDA_GPIO);
     panel_get_gpio(&scl, SCL_GPIO);
@@ -94,79 +94,79 @@ void HX8238_init(void)
 
     aic_delay_us(10);
 
-    HX8238_write(0x70, 0x0001);
-    HX8238_write(0x72, 0x6300);
+    hx8238_write(0x70, 0x0001);
+    hx8238_write(0x72, 0x6300);
 
-    HX8238_write(0x70, 0x0002);
-    HX8238_write(0x72, 0x0200);
+    hx8238_write(0x70, 0x0002);
+    hx8238_write(0x72, 0x0200);
 
-    HX8238_write(0x70, 0x0003);
-    HX8238_write(0x72, 0x6364);
+    hx8238_write(0x70, 0x0003);
+    hx8238_write(0x72, 0x6364);
 
-    HX8238_write(0x70, 0x0004);
-    HX8238_write(0x72, 0x0489);
+    hx8238_write(0x70, 0x0004);
+    hx8238_write(0x72, 0x0489);
 
-    HX8238_write(0x70, 0x0005);
-    HX8238_write(0x72, 0xBCC4);
+    hx8238_write(0x70, 0x0005);
+    hx8238_write(0x72, 0xBCC4);
 
-    HX8238_write(0x70, 0x000A);
-    HX8238_write(0x72, 0x4008);
+    hx8238_write(0x70, 0x000A);
+    hx8238_write(0x72, 0x4008);
 
-    HX8238_write(0x70, 0x000B);
-    HX8238_write(0x72, 0xD400);
+    hx8238_write(0x70, 0x000B);
+    hx8238_write(0x72, 0xD400);
 
-    HX8238_write(0x70, 0x000D);
-    HX8238_write(0x72, 0x3229);
+    hx8238_write(0x70, 0x000D);
+    hx8238_write(0x72, 0x3229);
 
-    HX8238_write(0x70, 0x000E);
-    HX8238_write(0x72, 0x3200);
+    hx8238_write(0x70, 0x000E);
+    hx8238_write(0x72, 0x3200);
 
-    HX8238_write(0x70, 0x000F);
-    HX8238_write(0x72, 0x0000);
+    hx8238_write(0x70, 0x000F);
+    hx8238_write(0x72, 0x0000);
 
-    HX8238_write(0x70, 0x0016);
-    HX8238_write(0x72, 0x9F80);
+    hx8238_write(0x70, 0x0016);
+    hx8238_write(0x72, 0x9F80);
 
-    HX8238_write(0x70, 0x0017);
-    HX8238_write(0x72, 0x2212);
+    hx8238_write(0x70, 0x0017);
+    hx8238_write(0x72, 0x2212);
 
-    HX8238_write(0x70, 0x001E);
-    HX8238_write(0x72, 0x00D2);
+    hx8238_write(0x70, 0x001E);
+    hx8238_write(0x72, 0x00D2);
 
-    HX8238_write(0x70, 0x0030);
-    HX8238_write(0x72, 0x0000);
+    hx8238_write(0x70, 0x0030);
+    hx8238_write(0x72, 0x0000);
 
-    HX8238_write(0x70, 0x0031);
-    HX8238_write(0x72, 0x0407);
+    hx8238_write(0x70, 0x0031);
+    hx8238_write(0x72, 0x0407);
 
-    HX8238_write(0x70, 0x0032);
-    HX8238_write(0x72, 0x0202);
+    hx8238_write(0x70, 0x0032);
+    hx8238_write(0x72, 0x0202);
 
-    HX8238_write(0x70, 0x0033);
-    HX8238_write(0x72, 0x0000);
+    hx8238_write(0x70, 0x0033);
+    hx8238_write(0x72, 0x0000);
 
-    HX8238_write(0x70, 0x0034);
-    HX8238_write(0x72, 0x0505);
+    hx8238_write(0x70, 0x0034);
+    hx8238_write(0x72, 0x0505);
 
-    HX8238_write(0x70, 0x0035);
-    HX8238_write(0x72, 0x0003);
+    hx8238_write(0x70, 0x0035);
+    hx8238_write(0x72, 0x0003);
 
-    HX8238_write(0x70, 0x0036);
-    HX8238_write(0x72, 0x0707);
+    hx8238_write(0x70, 0x0036);
+    hx8238_write(0x72, 0x0707);
 
-    HX8238_write(0x70, 0x0037);
-    HX8238_write(0x72, 0x0000);
+    hx8238_write(0x70, 0x0037);
+    hx8238_write(0x72, 0x0000);
 
-    HX8238_write(0x70, 0x003A);
-    HX8238_write(0x72, 0x0904);
+    hx8238_write(0x70, 0x003A);
+    hx8238_write(0x72, 0x0904);
 
-    HX8238_write(0x70, 0x003B);
-    HX8238_write(0x72, 0x0904);
+    hx8238_write(0x70, 0x003B);
+    hx8238_write(0x72, 0x0904);
 }
 
 static int panel_prepare(void)
 {
-    HX8238_init();
+    hx8238_init();
 
     return panel_default_prepare();
 }
@@ -180,7 +180,7 @@ static struct aic_panel_funcs panel_funcs = {
 };
 
 static struct display_timing hx8238_timing = {
-    .pixelclock = 15000000,
+    .pixelclock = 8000000,
     .hactive = 320,
     .hfront_porch = 20,
     .hback_porch = 12,