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https://gitee.com/Vancouver2017/luban-lite-t3e-pro.git
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107 lines
2.6 KiB
C
107 lines
2.6 KiB
C
/*
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* Copyright (c) 2022, Artinchip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <rtconfig.h>
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#include <stdbool.h>
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#include <string.h>
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#include <aic_core.h>
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#include <stdint.h>
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#include "aic_hal_mtop.h"
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#include "aic_hal_clk.h"
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void hal_mtop_irq_enable(struct aic_mtop_dev *phandle)
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{
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writel(0x1, phandle->reg_base + MTOP_IRQ_CTL);
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}
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int hal_mtop_init(struct aic_mtop_dev *phandle)
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{
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int ret;
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phandle->reg_base = MTOP_BASE;
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phandle->irq_num = MTOP_IRQn;
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phandle->clk_id = CLK_MTOP;
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phandle->grp = MTOP_GROUP_MAX;
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phandle->prt = MTOP_PORT_MAX;
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ret = hal_clk_enable_deassertrst(phandle->clk_id);
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if (ret) {
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hal_log_err("mtop enable clock deassert failed\n");
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return ret;
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}
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return 0;
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}
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int hal_mtop_deinit(struct aic_mtop_dev *phandle)
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{
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int ret;
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ret = hal_clk_disable_assertrst(phandle->clk_id);
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if (ret) {
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hal_log_err("mtop disable clock assert failed\n");
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return ret;
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}
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return 0;
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}
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void hal_mtop_enable(struct aic_mtop_dev *phandle)
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{
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uint32_t reg_value;
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reg_value = readl(phandle->reg_base + MTOP_CTL);
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reg_value |= MTOP_EN;
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writel(reg_value, phandle->reg_base + MTOP_CTL);
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}
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void hal_mtop_set_period_cnt(struct aic_mtop_dev *phandle, uint32_t period_cnt)
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{
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writel(period_cnt, phandle->reg_base + MTOP_TIME_CNT);
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}
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void hal_mtop_attach_callback(struct aic_mtop_dev *phandle, void *callback, void *arg)
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{
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phandle->callback = callback;
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phandle->arg = arg;
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}
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void hal_mtop_detach_callback(struct aic_mtop_dev *phandle)
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{
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phandle->callback = NULL;
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phandle->arg = NULL;
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}
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irqreturn_t hal_mtop_irq_handler(int irq_num, void *can_handle)
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{
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uint32_t i, j, pos, offset;
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struct aic_mtop_dev *phandle = (struct aic_mtop_dev *)can_handle;
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if (readl(MTOP_BASE + MTOP_IRQ_STA)) {
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for (i = 0; i < MTOP_GROUP_MAX; i++)
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for (j = 0; j < MTOP_PORT_MAX; j++) {
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/* calculate the corresponding position of the port in BITMAP */
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pos = group_id[i] * 8 + j;
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if ((1 << pos) & PORT_BITMAP) {
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offset = 0x100 + 0x100 * group_id[i] + 0x20 * j;
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phandle->port_bw[i * phandle->prt + j].wcnt =
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readl(phandle->reg_base + offset);
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phandle->port_bw[i * phandle->prt + j].rcnt =
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readl(phandle->reg_base + offset + 4);
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}
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}
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if (phandle->callback)
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phandle->callback(phandle, phandle->arg);
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writel(1, MTOP_BASE + MTOP_IRQ_STA);
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return 0;
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}
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return IRQ_HANDLED;
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}
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