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https://gitee.com/Vancouver2017/luban-lite-t3e-pro.git
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252 lines
9.3 KiB
C
252 lines
9.3 KiB
C
/*
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* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Authors: matteo <duanmt@artinchip.com>
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*/
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#ifndef _ARTINCHIP_HAL_SDMC_H_
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#define _ARTINCHIP_HAL_SDMC_H_
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#include <bouncebuf.h>
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#define SDMC_CLOCK_MIN 400000 /* 400KHz */
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#define FIFO_MIN 8
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#define FIFO_MAX 4096
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#define SDMC_TIMEOUT 2000000
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/* SDMC controller register */
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#define SDMC_BLKCNT 0x000
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#define SDMC_BLKSIZ 0x004
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#define SDMC_CMDARG 0x008
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#define SDMC_CMD 0x00c
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#define SDMC_RESP0 0x010
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#define SDMC_RESP1 0x014
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#define SDMC_RESP2 0x018
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#define SDMC_RESP3 0x01c
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#define SDMC_TTMC 0x020
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#define SDMC_TCBC 0x024
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#define SDMC_TFBC 0x028
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#define SDMC_CTRST 0x02c
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#define SDMC_HCTRL1 0x030
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#define SDMC_CLKCTRL 0x034
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#define SDMC_HCTRL2 0x038
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#define SDMC_INTEN 0x03c
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#define SDMC_INTST 0x040
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#define SDMC_OINTST 0x044
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#define SDMC_FIFOCFG 0x048
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#define SDMC_HINFO 0x050
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#define SDMC_PBUSCFG 0x080
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#define SDMC_IDMARCAP 0x084
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#define SDMC_IDMASADDR 0x088
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#define SDMC_IDMAST 0x08c
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#define SDMC_IDMAINTEN 0x090
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#define SDMC_IDMACDA 0x094
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#define SDMC_IDMACBA 0x098
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#define SDMC_CTC 0x100
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#define SDMC_DLYCTRL 0x104
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#define SDMC_EMCR 0x108
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#define SDMC_VERID 0x118
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#define SDMC_FIFO_DATA 0x200
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/* Command configure register defines */
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#define SDMC_CMD_START BIT(31)
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#define SDMC_CMD_USE_HOLD_REG BIT(29)
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#define SDMC_CMD_UPD_CLK BIT(21)
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#define SDMC_CMD_INIT BIT(15)
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#define SDMC_CMD_STOP BIT(14)
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#define SDMC_CMD_PRV_DAT_WAIT BIT(13)
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#define SDMC_CMD_SEND_STOP BIT(12)
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#define SDMC_CMD_DAT_WR BIT(10)
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#define SDMC_CMD_DAT_EXP BIT(9)
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#define SDMC_CMD_RESP_CRC BIT(8)
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#define SDMC_CMD_RESP_LEN BIT(7)
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#define SDMC_CMD_RESP_EXP BIT(6)
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/* Controller status register defines */
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#define SDMC_CTRST_FCNT(x) (((x) >> 17) & 0x1FFF)
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#define SDMC_CTRST_BUSY BIT(9)
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#define SDMC_CTRST_FIFO_FULL BIT(3)
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#define SDMC_CTRST_FIFO_EMPTY BIT(2)
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/* Host control 1 register defines */
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#define SDMC_HCTRL1_USE_IDMAC BIT(25)
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#define SDMC_HCTRL1_SEND_AS_CCSD BIT(10)
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#define SDMC_HCTRL1_DMA_EN BIT(5)
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#define SDMC_HCTRL1_INT_EN BIT(4)
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#define SDMC_HCTRL1_DMA_RESET BIT(2)
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#define SDMC_HCTRL1_FIFO_RESET BIT(1)
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#define SDMC_HCTRL1_RESET BIT(0)
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#define SDMC_HCTRL1_RESET_ALL \
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(SDMC_HCTRL1_RESET | SDMC_HCTRL1_FIFO_RESET | SDMC_HCTRL1_DMA_RESET)
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/* Clock control register defines */
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#define SDMC_CLKCTRL_LOW_PWR BIT(16)
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#define SDMC_CLKCTRL_DIV_SHIFT 8
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#define SDMC_CLKCTRL_DIV_MASK GENMASK(15, 8)
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#define SDMC_CLKCTRL_DIV_MAX \
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(SDMC_CLKCTRL_DIV_MASK >> SDMC_CLKCTRL_DIV_SHIFT)
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#define SDMC_CLKCTRL_EN BIT(0)
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/* Host control 2 register defines */
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#define SDMC_HCTRL2_BW_8BIT BIT(29)
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#define SDMC_HCTRL2_BW_4BIT BIT(28)
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#define SDMC_HCTRL2_BW_1BIT 0
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#define SDMC_HCTRL2_BW_SHIFT 28
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#define SDMC_HCTRL2_DDR_MODE BIT(16)
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#define SDMC_HCTRL2_VOLT_18V BIT(0)
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/* Card-type */
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#define SDMC_CTYPE_1BIT (0)
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#define SDMC_CTYPE_4BIT (0x1)
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#define SDMC_CTYPE_8BIT (0x2)
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#define SDMC_CTYPE_RESERVED (0x3)
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/* Data-rate */
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#define SDMC_SDR_MODE (0)
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#define SDMC_DDR_MODE (0x1)
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/* Interrupt status & enable register defines */
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#define SDMC_INT_ALL 0xffffffff
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#define SDMC_INT_FROM_SDIO BIT(16)
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#define SDMC_INT_EBE BIT(15)
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#define SDMC_INT_AUTO_CMD_DONE BIT(14)
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#define SDMC_INT_SBE BIT(13)
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#define SDMC_INT_HLE BIT(12)
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#define SDMC_INT_FRUN BIT(11)
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#define SDMC_INT_HTO BIT(10)
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#define SDMC_INT_DRTO BIT(9)
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#define SDMC_INT_RTO BIT(8)
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#define SDMC_INT_DCRC BIT(7)
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#define SDMC_INT_RCRC BIT(6)
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#define SDMC_INT_RXDR BIT(5)
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#define SDMC_INT_TXDR BIT(4)
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#define SDMC_INT_DAT_DONE BIT(3)
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#define SDMC_INT_CMD_DONE BIT(2)
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#define SDMC_INT_RESP_ERR BIT(1)
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#define SDMC_INT_CD BIT(0)
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#define SDMC_DATA_ERR (SDMC_INT_EBE | SDMC_INT_SBE | SDMC_INT_HLE | \
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SDMC_INT_FRUN | SDMC_INT_EBE | SDMC_INT_DCRC)
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#define SDMC_DATA_TOUT (SDMC_INT_HTO | SDMC_INT_DRTO)
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/* FIFO configuration register defines */
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#define MSIZE(x) ((x) << 28)
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#define RX_WMARK(x) ((x) << 16)
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#define TX_WMARK(x) (x)
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#define RX_WMARK_SHIFT 16
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#define RX_WMARK_MASK (0x7ff << RX_WMARK_SHIFT)
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/* Peripheral bus configuration register defines */
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#define SDMC_PBUSCFG_IDMAC_EN BIT(7)
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#define SDMC_PBUSCFG_IDMAC_FB BIT(1)
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#define SDMC_PBUSCFG_IDMAC_SWR BIT(0)
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/* Internal DMAC interrupt defines */
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#define SDMC_IDMAC_INT_AIS BIT(9)
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#define SDMC_IDMAC_INT_NIS BIT(8)
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#define SDMC_IDMAC_INT_CES BIT(5)
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#define SDMC_IDMAC_INT_DU BIT(4)
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#define SDMC_IDMAC_INT_FBE BIT(2)
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#define SDMC_IDMAC_INT_RI BIT(1)
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#define SDMC_IDMAC_INT_TI BIT(0)
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#define SDMC_IDMAC_INT_MASK (SDMC_IDMAC_INT_AIS | SDMC_IDMAC_INT_NIS | \
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SDMC_IDMAC_INT_CES | SDMC_IDMAC_INT_DU | \
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SDMC_IDMAC_INT_FBE | SDMC_IDMAC_INT_RI | \
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SDMC_IDMAC_INT_TI)
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#define SDMC_IDMAC_OWN BIT(31)
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#define SDMC_IDMAC_CH BIT(4)
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#define SDMC_IDMAC_FS BIT(3)
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#define SDMC_IDMAC_LD BIT(2)
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/* Card Threshold Control */
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#define SDMC_CTC_CARDTHR_SHIFT (16)
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#define SDMC_CTC_CARDTHR_MASK GENMASK(27, 16)
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#define SDMC_CTC_CARDRDTHR_EN BIT(0)
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#define SDMC_DLYCTRL_EXT_CLK_MUX_SHIFT 30
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#define SDMC_DLYCTRL_EXT_CLK_MUX_MASK GENMASK(31, 30)
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#define SDMC_DLYCTRL_EXT_CLK_MUX_1 2
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#define SDMC_DLYCTRL_EXT_CLK_MUX_2 1
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#define SDMC_DLYCTRL_EXT_CLK_MUX_4 0
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#define SDMC_DLYCTRL_CLK_DRV_PHA_MASK GENMASK(29, 28)
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#define SDMC_DLYCTRL_CLK_DRV_PHA_SHIFT 28
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#define SDMC_DLYCTRL_CLK_DRV_PHA_0 0
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#define SDMC_DLYCTRL_CLK_DRV_PHA_90 1
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#define SDMC_DLYCTRL_CLK_DRV_PHA_180 2
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#define SDMC_DLYCTRL_CLK_DRV_PHA_270 3
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#define SDMC_DLYCTRL_CLK_DRV_DLY_MASK GENMASK(27, 23)
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#define SDMC_DLYCTRL_CLK_DRV_DLY_SHIFT 23
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#define SDMC_DLYCTRL_CLK_SMP_PHA_MASK GENMASK(22, 21)
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#define SDMC_DLYCTRL_CLK_SMP_PHA_SHIFT 21
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#define SDMC_DLYCTRL_CLK_SMP_PHA_0 0
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#define SDMC_DLYCTRL_CLK_SMP_PHA_90 1
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#define SDMC_DLYCTRL_CLK_SMP_PHA_180 2
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#define SDMC_DLYCTRL_CLK_SMP_PHA_270 3
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#define SDMC_DLYCTRL_CLK_DRV_DLY_MAX \
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(SDMC_DLYCTRL_CLK_DRV_DLY_MASK >> SDMC_DLYCTRL_CLK_DRV_DLY_SHIFT)
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#define SDMC_DLYCTRL_CLK_SMP_DLY_MASK GENMASK(20, 16)
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#define SDMC_DLYCTRL_CLK_SMP_DLY_SHIFT 16
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#define SDMC_DLYCTRL_CLK_SMP_DLY_MAX \
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(SDMC_DLYCTRL_CLK_SMP_DLY_MASK >> SDMC_DLYCTRL_CLK_SMP_DLY_SHIFT)
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/* quirks */
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#define SDMC_QUIRK_DISABLE_SMU (1 << 0)
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struct aic_sdmc_idma_desc {
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u32 flags;
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u32 cnt;
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u32 addr;
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u32 next_addr;
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} __aligned(8);
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struct aic_sdmc_host {
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volatile void *base;
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u32 is_sdio;
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u32 fifoth_val;
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#ifdef AIC_SDMC_IRQ_MODE
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aicos_sem_t complete;
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#endif
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};
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void hal_sdmc_idma_update_intstat(struct aic_sdmc_host *host);
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int hal_sdmc_idma_start(struct aic_sdmc_host *host, u32 size, u32 read,
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u32 *buf, struct bounce_buffer *bbstate);
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int hal_sdmc_idma_stop(struct aic_sdmc_host *host,
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struct bounce_buffer *bbstate, u32 read);
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void hal_sdmc_idma_disable(struct aic_sdmc_host *host);
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u8 hal_sdmc_get_idma_status(struct aic_sdmc_host *host);
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void hal_sdmc_idma_prepare(struct aic_sdmc_host *host,
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u32 blksize, u32 blks,
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struct aic_sdmc_idma_desc *cur_idma,
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void *bounce_buffer);
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int hal_sdmc_data_rx(struct aic_sdmc_host *host, u32 *buf, u32 size);
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int hal_sdmc_data_tx(struct aic_sdmc_host *host, u32 *buf, u32 size);
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u32 hal_sdmc_int_stat(struct aic_sdmc_host *host);
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void hal_sdmc_int_clr(struct aic_sdmc_host *host, u32 mask);
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int hal_sdmc_is_busy(struct aic_sdmc_host *host);
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void hal_sdmc_set_blk(struct aic_sdmc_host *host, u32 blksize, u32 blks);
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void hal_sdmc_set_arg(struct aic_sdmc_host *host, u32 arg);
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void hal_sdmc_set_cmd(struct aic_sdmc_host *host, u32 cmd);
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u32 hal_sdmc_wait_cmd_started(struct aic_sdmc_host *host);
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void hal_sdmc_get_rsp(struct aic_sdmc_host *host, u32 *buf, u32 all);
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void aic_sdmc_set_ext_clk_mux(struct aic_sdmc_host *host, u32 mux);
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void hal_sdmc_set_phase(struct aic_sdmc_host *host, u32 drv, u32 smp);
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void hal_sdmc_set_buswidth(struct aic_sdmc_host *host, u32 buswidth);
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void hal_sdmc_set_ddrmode(struct aic_sdmc_host *host, u32 ddr);
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void hal_sdmc_clk_disable(struct aic_sdmc_host *host);
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void hal_sdmc_clk_enable(struct aic_sdmc_host *host);
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void hal_sdmc_sdio_irq_enable(struct aic_sdmc_host *host, u32 en);
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void hal_sdmc_set_div(struct aic_sdmc_host *host, u32 div);
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void hal_sdmc_fifo_init(struct aic_sdmc_host *host, u32 *thd);
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int hal_sdmc_reset(struct aic_sdmc_host *host, u32 value);
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void hal_sdmc_init(struct aic_sdmc_host *host);
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#endif
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