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https://gitee.com/Vancouver2017/luban-lite-t3e-pro.git
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139 lines
3.4 KiB
C
139 lines
3.4 KiB
C
/*
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* Copyright (c) 2023, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Authors: Mingfeng.Li <mingfeng.li@artinchip.com>
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*/
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#ifndef _AIC_HAL_XSPI_
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#define _AIC_HAL_XSPI_
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#include <aic_common.h>
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#include <stdbool.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define HAL_XSPI_MAX_FREQ_HZ 445500000
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#define HAL_XSPI_MIN_FREQ_HZ 49500000
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#define BOUNDARY_2K 0
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#define BOUNDARY_1K 1
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struct hal_xspi_state;
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typedef struct hal_xspi_state hal_xspi_handle;
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typedef void (*hal_xspi_async_cb)(hal_xspi_handle *h, void *priv);
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typedef struct hal_xspi_proto_cfg hal_xspi_proto_cfg_t;
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struct hal_xspi_config {
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u32 idx;
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u32 clk_in_hz;
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u32 clk_id;
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u32 cs0_port;
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u32 cs1_port;
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bool bit_mode;
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bool wire3_en;
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bool lsb_en;
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bool cs_auto;
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u8 cs_polarity;
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u8 cpol;
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u8 cpha;
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};
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struct hal_xspi_dma_config {
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u32 port_id;
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u32 tx_bus_width;
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u32 tx_max_burst;
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u32 rx_bus_width;
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u32 rx_max_burst;
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};
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struct hal_xspi_transfer {
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u8 *tx_data;
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u8 *rx_data;
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u32 data_len;
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};
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struct hal_xspi_proto_cfg {
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u8 mode;
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u8 clk_mode;
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u8 parallel_mode;
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u8 wr_cmd_clk_mode;
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u8 wr_cmd_lines;
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u8 wr_cmd_val;
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u8 rd_cmd_clk_mode;
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u8 rd_cmd_lines;
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u8 rd_cmd_val;
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u8 addr_clk_mode;
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u8 addr_lines;
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u8 addr_width;
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u8 wr_dummy;
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u8 rd_dummy;
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u8 wr_cnt_lines;
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u32 wr_cnt;
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u8 rd_cnt_lines;
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u32 rd_cnt;
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};
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/*
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* HAL XSPI internal state, HAL user should not modify it directly
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*/
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struct hal_xspi_state {
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u32 idx;
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hal_xspi_async_cb cb;
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void *cb_priv;
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u32 status;
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u32 clk_id;
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u32 bus_hz;
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u32 bus_width;
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struct hal_xspi_dma_config dma_cfg;
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void *dma_tx;
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void *dma_rx;
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u8 *async_tx; /* Used in Async Non-DMA mode */
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u8 *async_rx; /* Used in Async Non-DMA mode */
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u32 async_tx_remain; /* Used in Async Non-DMA mode */
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u32 async_rx_remain; /* Used in Async Non-DMA mode */
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u32 work_mode;
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u32 done_mask;
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};
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int hal_xspi_init(hal_xspi_handle *h, struct hal_xspi_config *cfg);
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int hal_xspi_reset_clk(hal_xspi_handle *h, u32 reset_clock);
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int hal_xspi_set_cmd_width(hal_xspi_handle *h, u8 ddr_sdr_mode, u8 lines);
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int hal_xspi_set_cmd_width(hal_xspi_handle *h, u8 ddr_sdr_mode, u8 lines);
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int hal_xspi_set_cmd(hal_xspi_handle *h, u8 ddr_sdr_mode, u8 cmd);
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int hal_xspi_set_addr_width(hal_xspi_handle *h, u8 ddr_sdr_mode, u8 lines, u8 bw_3_4_bytes);
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int hal_xspi_set_addr(hal_xspi_handle *h, u8 addr);
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int hal_xspi_set_dummy(hal_xspi_handle *h, u8 lines, u8 dummy);
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int hal_xspi_set_write_cnt(hal_xspi_handle *h, u8 ddr_sdr_mode, u8 lines, u32 count);
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int hal_xspi_set_read_cnt(hal_xspi_handle *h, u8 ddr_sdr_mode, u8 lines, u32 count);
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int hal_xspi_start_transfer(hal_xspi_handle *h);
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int hal_xspi_transfer_cpu_sync(hal_xspi_handle *h, struct hal_xspi_transfer *t);
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int hal_xspi_xip_cfg(hal_xspi_handle *h, hal_xspi_proto_cfg_t xip_proto_cfg);
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int hal_xspi_xip_enable(hal_xspi_handle *h);
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int hal_xspi_dll_training(hal_xspi_handle *h, u8 sel, u8 reg_icp, void *psram_buf, u32 len);
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int hal_xspi_set_dll_ctl(hal_xspi_handle *h, u8 sel, u8 reg_icp, u8 phase_sel);
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int hal_xspi_set_phase_sel(hal_xspi_handle *h, u8 sel, u8 phase_sel);
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int hal_xspi_set_cs(hal_xspi_handle *h, u8 sel);
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int hal_xspi_set_boudary(hal_xspi_handle *h, u8 by);
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int hal_xspi_set_parallel_mode(hal_xspi_handle *h, u8 mode);
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int hal_xspi_set_timeout(hal_xspi_handle *h, u32 timeout);
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#ifdef __cplusplus
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}
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#endif
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#endif
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