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https://gitee.com/Vancouver2017/luban-lite-t3e-pro.git
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320 lines
8.0 KiB
C
320 lines
8.0 KiB
C
/*
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* Copyright (c) 2022-2023, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Authors: matteo <duanmt@artinchip.com>
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*/
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#include "aic_core.h"
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#include "aic_hal_clk.h"
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#include "hal_adcim.h"
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/* Register of ADCIM */
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#define ADCIM_MCSR 0x000
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#define ADCIM_CALCSR 0x004
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#define ADCIM_FIFOSTS 0x008
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#define ADCIM_VERSION 0xFFC
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#define ADCIM_MCSR_BUSY BIT(16)
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#define ADCIM_MCSR_SEMFLAG_SHIFT 8
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#define ADCIM_MCSR_SEMFLAG_MASK GENMASK(15, 8)
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#define ADCIM_MCSR_CHN_MASK GENMASK(3, 0)
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#define ADCIM_CALCSR_CALVAL_UPD BIT(31)
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#define ADCIM_CALCSR_CALVAL_SHIFT 16
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#define ADCIM_CALCSR_CALVAL_MASK GENMASK(27, 16)
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#define ADCIM_CALCSR_ADC_ACQ_SHIFT 8
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#define ADCIM_CALCSR_ADC_ACQ_MASK GENMASK(15, 8)
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#define ADCIM_CALCSR_DCAL_MASK BIT(1)
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#define ADCIM_CALCSR_CAL_ENABLE BIT(0)
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#define ADCIM_FIFOSTS_ADC_ARBITER_IDLE BIT(6)
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#define ADCIM_FIFOSTS_FIFO_ERR BIT(5)
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#define ADCIM_FIFOSTS_CTR_MASK GENMASK(4, 0)
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#define ADCDM_CAL_ADC_STANDARD_VAL 0x800
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#define ADCIM_CAL_ADC_VAL_OFFSET 0X32
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#ifdef AIC_ADCIM_DM_DRV
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#define ADCDM_RTP_CFG 0x03F0
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#define ADCDM_RTP_STS 0x03F4
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#define ADCDM_SRAM_CTL 0x03F8
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#define ADCDM_SRAM_BASE 0x0400
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#define ADCDM_RTP_CAL_VAL_SHIFT 16
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#define ADCDM_RTP_CAL_VAL_MASK GENMASK(27, 16)
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#define ADCDM_RTP_PDET BIT(0)
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#define ADCDM_RTP_DRV_SHIFT 4
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#define ADCDM_RTP_DRV_MASK GENMASK(7, 4)
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#define ADCDM_RTP_VPSEL_SHIFT 2
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#define ADCDM_RTP_VPSEL_MASK GENMASK(3, 2)
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#define ADCDM_RTP_VNSEL_MASK GENMASK(1, 0)
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#define ADCDM_SRAM_CLR_SHIFT 16
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#define ADCDM_SRAM_CLR(n) (1 << ((n) + ADCDM_SRAM_CLR_SHIFT))
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#define ADCDM_SRAM_MODE_SHIFT 8
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#define ADCDM_SRAM_MODE BIT(8)
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#define ADCDM_SRAM_SEL_MASK GENMASK(3, 0)
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#define ADCDM_SRAM_SEL(n) (n)
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#define ADCDM_SRAM_SIZE (512 * 4)
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#define ADCDM_CHAN_NUM 16
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enum adcdm_sram_mode {
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ADCDM_NORMAL_MODE = 0,
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ADCDM_DEBUG_MODE = 1
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};
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#endif
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struct adcim_dev {
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#ifdef AIC_ADCIM_DM_DRV
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u32 dm_cur_chan;
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#endif
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int usr_cnt;
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};
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#ifdef AIC_ADCIM_DM_DRV
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static struct adcim_dev g_adcim_dev = {0};
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#endif
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static inline void adcim_writel(u32 val, int reg)
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{
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writel(val, ADCIM_BASE + reg);
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}
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static inline u32 adcim_readl(int reg)
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{
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return readl(ADCIM_BASE + reg);
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}
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int hal_adcim_calibration_set(unsigned int val)
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{
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int cal;
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if (val > 2048) {
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pr_err("The calibration value %d is too big\n", val);
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return -EINVAL;
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}
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cal = adcim_readl(ADCIM_CALCSR);
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cal = (cal & ~ADCIM_CALCSR_CALVAL_MASK)
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| (val << ADCIM_CALCSR_CALVAL_SHIFT);
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cal = cal | ADCIM_CALCSR_CALVAL_UPD;
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adcim_writel(cal, ADCIM_CALCSR);
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return 0;
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}
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int hal_adcim_auto_calibration(int adc_val, int st_voltage, int scale,
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int adc_max_val)
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{
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u32 flag = 1;
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u32 data = 0;
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int new_voltage = 0;
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adcim_writel(0x083F2f03, ADCIM_CALCSR);//auto cal
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do {
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flag = adcim_readl(ADCIM_CALCSR) & 0x00000001;
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} while (flag);
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data = (adcim_readl(ADCIM_CALCSR) >> 16) & 0xfff;
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if (adc_val) {
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new_voltage = (adc_val + ADCDM_CAL_ADC_STANDARD_VAL - data + ADCIM_CAL_ADC_VAL_OFFSET) * st_voltage * scale / adc_max_val;
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}
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return new_voltage;
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}
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void adcim_status_show(void)
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{
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int mcsr;
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int fifo;
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int version;
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#ifdef AIC_ADCIM_DM_DRV
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int rtp_cfg, rtp_sts, sram_ctl;
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#endif
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mcsr = adcim_readl(ADCIM_MCSR);
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fifo = adcim_readl(ADCIM_FIFOSTS);
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version = adcim_readl(ADCIM_VERSION);
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#ifdef AIC_ADCIM_DM_DRV
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rtp_cfg = adcim_readl(ADCDM_RTP_CFG);
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rtp_sts = adcim_readl(ADCDM_RTP_STS);
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sram_ctl = adcim_readl(ADCDM_SRAM_CTL);
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#endif
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hal_log_info("In ADCIM V%d.%02d:\n"
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"Busy state: %d\n"
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"Semflag: %d\n"
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"Current Channel: %d\n"
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"ADC Arbiter Idel: %d\n"
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"FIFO Error: %d\n"
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"FIFO Counter: %d\n"
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#ifdef AIC_ADCIM_DM_DRV
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"\nIn DM:\nMode: %s, Current channel: %d/%ld\n"
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"Calibration val: %ld\n"
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"RTP PDET: %ld, DRV: %ld, VPSEL: %ld, VNSEL: %ld\n"
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#endif
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, version >> 8, version & 0xff,
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(mcsr & ADCIM_MCSR_BUSY) ? 1 : 0,
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(mcsr & ADCIM_MCSR_SEMFLAG_MASK)
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>> ADCIM_MCSR_SEMFLAG_SHIFT,
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mcsr & ADCIM_MCSR_CHN_MASK,
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fifo & ADCIM_FIFOSTS_ADC_ARBITER_IDLE ? 1 : 0,
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fifo & ADCIM_FIFOSTS_FIFO_ERR ? 1 : 0,
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fifo & ADCIM_FIFOSTS_CTR_MASK
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#ifdef AIC_ADCIM_DM_DRV
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, sram_ctl & ADCDM_SRAM_MODE ? "Debug" : "Normal",
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g_adcim_dev.dm_cur_chan, sram_ctl & ADCDM_SRAM_SEL_MASK,
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(rtp_cfg & ADCDM_RTP_CAL_VAL_MASK)
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>> ADCDM_RTP_CAL_VAL_SHIFT,
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rtp_cfg & ADCDM_RTP_PDET,
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(rtp_sts & ADCDM_RTP_DRV_MASK) >> ADCDM_RTP_DRV_SHIFT,
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(rtp_sts & ADCDM_RTP_VPSEL_MASK)
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>> ADCDM_RTP_VPSEL_SHIFT,
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rtp_sts & ADCDM_RTP_VNSEL_MASK
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#endif
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);
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}
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void adcim_calibration_show(void)
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{
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int cal;
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cal = adcim_readl(ADCIM_CALCSR);
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pr_info("Calibration Enable: %d\n Current value: %d\nADC ACQ: %d\n",
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(cal & ADCIM_CALCSR_CAL_ENABLE) ? 0 : 1,
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(cal & ADCIM_CALCSR_CALVAL_MASK) >> ADCIM_CALCSR_CALVAL_SHIFT,
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(cal & ADCIM_CALCSR_ADC_ACQ_MASK) >> ADCIM_CALCSR_ADC_ACQ_SHIFT);
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}
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#ifdef AIC_ADCIM_DM_DRV
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void hal_dm_chan_show(void)
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{
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pr_info("Current chan: %d/%ld\n", g_adcim_dev.dm_cur_chan,
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adcim_readl(ADCDM_SRAM_CTL) & ADCDM_SRAM_SEL_MASK);
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}
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s32 hal_dm_chan_store(u32 val)
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{
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int ret;
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if (val >= ADCDM_CHAN_NUM) {
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hal_log_err("Invalid channel number %u\n", val);
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return 0;
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}
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g_adcim_dev.dm_cur_chan = val;
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ret = adcim_readl(ADCDM_SRAM_CTL);
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ret &= ~ADCDM_SRAM_SEL_MASK;
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ret |= val;
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adcim_writel(ret, ADCDM_SRAM_CTL);
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return 0;
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}
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void hal_adcdm_rtp_down_store(u32 val)
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{
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int ret;
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ret = adcim_readl(ADCDM_RTP_CFG);
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if (val)
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ret &= ~ADCDM_RTP_PDET;
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else
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ret |= ADCDM_RTP_PDET;
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adcim_writel(ret, ADCDM_RTP_CFG);
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}
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static void adcdm_sram_clear(u32 chan)
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{
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u32 val = 0;
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val = adcim_readl(ADCDM_SRAM_CTL);
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val |= ADCDM_SRAM_CLR(chan);
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adcim_writel(val, ADCDM_SRAM_CTL);
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val &= ~ADCDM_SRAM_CLR(chan);
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adcim_writel(val, ADCDM_SRAM_CTL);
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}
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static void adcdm_sram_mode(enum adcdm_sram_mode mode)
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{
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u32 val = 0;
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val = adcim_readl(ADCDM_SRAM_CTL);
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if (mode)
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val |= mode << ADCDM_SRAM_MODE_SHIFT;
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else
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val &= ~ADCDM_SRAM_MODE;
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adcim_writel(val, ADCDM_SRAM_CTL);
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}
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static void adcdm_sram_select(u32 chan)
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{
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u32 val = 0;
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val = adcim_readl(ADCDM_SRAM_CTL);
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val &= ~ADCDM_SRAM_SEL_MASK;
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val |= chan;
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adcim_writel(val, ADCDM_SRAM_CTL);
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}
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ssize_t hal_adcdm_sram_write(int *buf, u32 offset, size_t count)
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{
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int i;
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if (count + offset > ADCDM_SRAM_SIZE)
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return 0;
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hal_adcim_probe();
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adcdm_sram_mode(ADCDM_DEBUG_MODE);
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adcdm_sram_select(g_adcim_dev.dm_cur_chan);
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for (i = 0; i < count; i++) {
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adcim_writel(buf[i], ADCDM_SRAM_BASE + i * 4);
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}
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adcdm_sram_mode(ADCDM_NORMAL_MODE);
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for (i = 0; i < ADCDM_CHAN_NUM; i++)
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adcdm_sram_clear(i);
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return count;
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}
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#endif
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s32 hal_adcim_probe(void)
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{
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s32 ret = 0;
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static s32 inited = 0;
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if (inited) {
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hal_log_info("ADCIM is already inited\n");
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return 0;
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}
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#ifdef AIC_ADCIM_DRV_V11
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ret = hal_clk_set_freq(CLK_ADCIM, 48000000);
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if (ret < 0) {
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hal_log_err("Failed to set ADCIM clk\n");
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return -1;
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}
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#endif
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ret = hal_clk_enable(CLK_ADCIM);
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if (ret < 0) {
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hal_log_err("ADCIM clk enable failed!\n");
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return -1;
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}
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ret = hal_clk_enable_deassertrst(CLK_ADCIM);
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if (ret < 0) {
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hal_log_err("ADCIM reset deassert failed!\n");
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return -1;
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}
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inited = 1;
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return 0;
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}
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