mirror of
https://gitee.com/Vancouver2017/luban-lite-t3e-pro.git
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263 lines
7.6 KiB
C
263 lines
7.6 KiB
C
/*
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* Copyright (c) 2022, Artinchip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _AIC_HAL_QSPI_
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#define _AIC_HAL_QSPI_
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#include <aic_common.h>
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#include <stdbool.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define HAL_QSPI_INVALID (0xFFFFFFFF)
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#define HAL_QSPI_BUS_WIDTH_SINGLE 1
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#define HAL_QSPI_BUS_WIDTH_DUAL 2
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#define HAL_QSPI_BUS_WIDTH_QUAD 4
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#define HAL_QSPI_MAX_FREQ_HZ 133000000
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#define HAL_QSPI_MIN_FREQ_HZ 3000
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#define HAL_QSPI_CPOL_ACTIVE_HIGH 0
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#define HAL_QSPI_CPOL_ACTIVE_LOW 1
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#define HAL_QSPI_CPHA_FIRST_EDGE 0
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#define HAL_QSPI_CPHA_SECOND_EDGE 1
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#define HAL_QSPI_CS_POL_VALID_HIGH 0
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#define HAL_QSPI_CS_POL_VALID_LOW 1
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#define HAL_QSPI_RX_FIFO 0
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#define HAL_QSPI_TX_FIFO 1
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struct qspi_master_state;
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struct qspi_slave_state;
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typedef struct qspi_master_state qspi_master_handle;
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typedef struct qspi_slave_state qspi_slave_handle;
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typedef void (*qspi_master_async_cb)(qspi_master_handle *h, void *priv);
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typedef void (*qspi_slave_async_cb)(qspi_slave_handle *h, void *priv);
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struct qspi_master_config {
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u32 idx;
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u32 clk_in_hz;
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u32 clk_id;
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bool bit_mode;
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bool wire3_en;
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bool lsb_en;
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bool cs_auto;
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u8 cs_polarity;
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u8 cpol;
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u8 cpha;
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};
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struct qspi_master_dma_config {
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u32 port_id;
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u32 tx_bus_width;
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u32 tx_max_burst;
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u32 rx_bus_width;
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u32 rx_max_burst;
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};
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struct qspi_slave_config {
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u32 idx;
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u32 clk_in_hz;
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u32 clk_id;
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bool bit_mode;
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bool wire3_en;
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bool lsb_en;
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bool cs_auto;
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u8 cs_polarity;
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u8 cpol;
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u8 cpha;
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};
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struct qspi_slave_idma_config {
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u32 tx_bus_width;
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u32 tx_max_burst;
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u32 rx_bus_width;
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u32 rx_max_burst;
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};
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struct qspi_transfer {
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u8 *tx_data;
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u8 *rx_data;
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u32 data_len;
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};
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#define HAL_QSPI_STATUS_OK (0)
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#define HAL_QSPI_STATUS_IN_PROGRESS (0x1UL << 0)
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#define HAL_QSPI_STATUS_RX_UNDER_RUN (0x1UL << 1)
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#define HAL_QSPI_STATUS_RX_OVER_FLOW (0x1UL << 2)
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#define HAL_QSPI_STATUS_TX_UNDER_RUN (0x1UL << 3)
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#define HAL_QSPI_STATUS_TX_OVER_FLOW (0x1UL << 4)
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#define HAL_QSPI_STATUS_RX_READY (0x1UL << 5)
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#define HAL_QSPI_STATUS_CS_INVALID (0x1UL << 6)
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#define HAL_QSPI_STATUS_TRAN_DONE (0x1UL << 31)
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/*
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* HAL QSPI internal state, HAL user should not modify it directly
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*/
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struct qspi_master_state {
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u32 idx;
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qspi_master_async_cb cb;
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void *cb_priv;
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u32 status;
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u32 clk_id;
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u32 bus_hz;
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u32 bus_width;
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struct qspi_master_dma_config dma_cfg;
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void *dma_tx;
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void *dma_rx;
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u8 *async_tx; /* Used in Async Non-DMA mode */
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u8 *async_rx; /* Used in Async Non-DMA mode */
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u32 async_tx_remain; /* Used in Async Non-DMA mode */
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u32 async_rx_remain; /* Used in Async Non-DMA mode */
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u32 work_mode;
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u32 done_mask;
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bool bit_mode;
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};
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struct qspi_slave_state {
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u32 idx;
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qspi_slave_async_cb cb;
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void *cb_priv;
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u32 status;
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u32 clk_id;
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u32 bus_hz;
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u32 bus_width;
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u8 *async_tx; /* Used in Async Non-DMA mode */
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u8 *async_rx; /* Used in Async Non-DMA mode */
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u32 async_tx_wcnt; /* Used in Async mode */
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u32 async_tx_remain; /* Used in Async mode */
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u32 async_rx_remain; /* Used in Async mode */
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u32 async_tx_count; /* Used in Async mode */
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u32 async_rx_count; /* Used in Async mode */
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u32 work_mode;
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u32 done_mask;
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};
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struct qspi_bm_transfer {
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u8 *tx_data;
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u8 *rx_data;
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u32 rx_len;
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u32 tx_len;
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};
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#ifdef AIC_QSPI_DRV_V11
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/*
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* SPI NOR device's wrap bits setting value.
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* Should check SPI NOR datasheet to get these values.
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*/
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struct qspi_xip_wrap_bits {
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/*
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* When config SPI controller select to use fixed wrap length, should
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* set the selected wrap bits value to it.
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*/
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u8 fixed_len;
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/*
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* Wrap bits value to disable wrap length
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*/
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u8 disable;
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/*
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* Wrap bits value to select wrap length 64bytes
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*/
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u8 auto_wl64;
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/*
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* Wrap bits value to select wrap length 32bytes
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*/
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u8 auto_wl32;
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/*
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* Wrap bits value to select wrap length 16bytes
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*/
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u8 auto_wl16;
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/*
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* Wrap bits value to select wrap length 8bytes
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*/
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u8 auto_wl8;
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};
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#define HAL_XIP_BURST_WRAPPED_DISABLED 0x00
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#define HAL_XIP_BURST_WRAPPED_WITH_FIXED_LEN 0x01
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#define HAL_XIP_BURST_WRAPPED_WITH_AUTO_SEL_LEN 0x02
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/*
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* When Cache enabled, should setup read burst
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*/
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struct qspi_xip_burst_cfg {
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u8 cmd_set_burst; /* CMD to set burst with wrap or linear, 77h or C0h */
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u8 cmd_dummy_byte; /* Dummy byte fot set burst command */
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u8 cmd_bits_width; /* When CMD is C0h, bits width is needed to set */
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u8 wrap_en; /* 00: disable, 01 wrap with fixed len, 02 wrap with auto len */
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struct qspi_xip_wrap_bits wrap;
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};
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struct qspi_xip_read_cmd_mode_byte {
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/*
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* Mode byte code value to set read command bypass mode,
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* User should check SPI NOR datasheet and set it.
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*/
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u8 bypass;
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/*
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* Mode byte code value to set read command normal mode,
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* User should check SPI NOR datasheet and set it.
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*/
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u8 normal;
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};
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struct qspi_xip_read_cfg {
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/*
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* QIO or QPI read command value
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*/
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u8 read_cmd;
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/*
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* Read command's dummy byte.
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* User should check SPI NOR datasheet and set it.
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*/
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u8 dummy_byte;
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u8 addr_mode; /* 0: 3byte address, 1: 4byte address */
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/*
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* When CPU cache is disabled, user can select to enable read command bypass mode
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*/
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u8 read_cmd_bypass_en;
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struct qspi_xip_read_cmd_mode_byte mode;
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};
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int hal_qspi_master_set_qio_mode(qspi_master_handle *h);
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void hal_qspi_master_set_cs_owner(qspi_master_handle *h, u8 soft_hw);
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void hal_qspi_master_set_xip_burst_cfg(qspi_master_handle *h, struct qspi_xip_burst_cfg *cfg);
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void hal_qspi_master_set_xip_read_cfg(qspi_master_handle *h, struct qspi_xip_read_cfg *cfg);
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void hal_qspi_master_xip_enable(qspi_master_handle *h, bool enable);
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int hal_qspi_slave_init(qspi_slave_handle *h, struct qspi_slave_config *cfg);
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int hal_qspi_slave_deinit(qspi_slave_handle *h);
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int hal_qspi_slave_set_bus_width(qspi_slave_handle *h, u32 bus_width);
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int hal_qspi_slave_idma_config(qspi_slave_handle *h, struct qspi_slave_idma_config *cfg);
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int hal_qspi_slave_register_cb(qspi_slave_handle *h, qspi_slave_async_cb cb, void *priv);
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int hal_qspi_slave_get_status(qspi_slave_handle *h);
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void hal_qspi_slave_irq_handler(qspi_slave_handle *h);
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int hal_qspi_slave_transfer_async(qspi_slave_handle *h, struct qspi_transfer *t);
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int hal_qspi_slave_transfer_abort(qspi_slave_handle *h);
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int hal_qspi_slave_transfer_count(qspi_slave_handle *h);
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void hal_qspi_slave_fifo_reset(qspi_slave_handle *h, u32 fifo);
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#endif //AIC_QSPI_DRV_V11
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int hal_qspi_master_init(qspi_master_handle *h, struct qspi_master_config *cfg);
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int hal_qspi_master_deinit(qspi_master_handle *h);
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int hal_qspi_master_set_cs(qspi_master_handle *h, u32 cs_num, bool enable);
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int hal_qspi_master_set_bus_freq(qspi_master_handle *h, u32 bus_hz);
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int hal_qspi_master_set_bus_width(qspi_master_handle *h, u32 bus_width);
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int hal_qspi_master_transfer_sync(qspi_master_handle *h, struct qspi_transfer *t);
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int hal_qspi_master_dma_config(qspi_master_handle *h, struct qspi_master_dma_config *cfg);
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int hal_qspi_master_register_cb(qspi_master_handle *h, qspi_master_async_cb cb, void *priv);
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int hal_qspi_master_transfer_async(qspi_master_handle *h, struct qspi_transfer *t);
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int hal_qspi_master_get_status(qspi_master_handle *h);
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void hal_qspi_master_irq_handler(qspi_master_handle *h);
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void hal_qspi_master_fifo_reset(qspi_master_handle *h, u32 fifo);
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int hal_qspi_master_transfer_bit_mode(qspi_master_handle *h, struct qspi_bm_transfer *t);
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#ifdef __cplusplus
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}
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#endif
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#endif
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