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https://gitee.com/Vancouver2017/luban-lite-t3e-pro.git
synced 2025-12-14 18:38:55 +00:00
138 lines
3.4 KiB
C
138 lines
3.4 KiB
C
#include <string.h>
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#include <finsh.h>
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#include <rtconfig.h>
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#include <rtdevice.h>
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#include <aic_core.h>
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#include <aic_hal.h>
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#include <hal_qspi.h>
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#include <rtthread.h>
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struct spi_pinmux {
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unsigned char func;
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unsigned char bias;
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unsigned char drive;
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char *name;
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};
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/* Please change your pinmux setting according your board */
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static struct spi_pinmux spi_pinmux_config[] = {
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/* qspi1 */
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{ 3, PIN_PULL_UP, 3, "PD.4" }, // CS, default set to high
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{ 3, PIN_PULL_UP, 3, "PD.5" },
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{ 3, PIN_PULL_UP, 3, "PD.6" }, // SI
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{ 3, PIN_PULL_UP, 7, "PD.7" }, // CLK
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{ 3, PIN_PULL_UP, 3, "PD.8" },
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{ 3, PIN_PULL_UP, 3, "PD.9" },
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/* qspi2 */
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{ 3, PIN_PULL_UP, 3, "PB.6" },
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{ 3, PIN_PULL_UP, 3, "PB.7" },
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{ 3, PIN_PULL_UP, 3, "PB.8" },
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{ 3, PIN_PULL_UP, 3, "PB.9" },
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{ 3, PIN_PULL_UP, 3, "PB.10" },
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{ 3, PIN_PULL_UP, 3, "PB.11" },
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/* qspi3 */
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{ 3, PIN_PULL_UP, 3, "PD.0" },
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{ 3, PIN_PULL_UP, 3, "PD.1" }, //CS, default set to high
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{ 3, PIN_PULL_UP, 3, "PD.2" },
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{ 3, PIN_PULL_UP, 3, "PD.3" },
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};
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static u32 qspi_clk_ids[4] = {CLK_QSPI0, CLK_QSPI1, CLK_QSPI2, CLK_QSPI3};
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static u32 qspi_irq_num[] = {QSPI0_IRQn, QSPI1_IRQn, QSPI2_IRQn, QSPI3_IRQn};
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static u32 qspi_input_clk[4] = {
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#ifdef AIC_USING_QSPI0
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[0] = AIC_DEV_QSPI0_MAX_SRC_FREQ_HZ,
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#endif
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#ifdef AIC_USING_QSPI1
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[1] = AIC_DEV_QSPI1_MAX_SRC_FREQ_HZ,
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#endif
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#ifdef AIC_USING_QSPI2
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[2] = AIC_DEV_QSPI2_MAX_SRC_FREQ_HZ,
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#endif
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#ifdef AIC_USING_QSPI3
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[3] = AIC_DEV_QSPI3_MAX_SRC_FREQ_HZ,
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#endif
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};
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void test_qspi_slave_set_pinmux(void)
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{
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uint32_t i = 0;
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long pin = 0;
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unsigned int g;
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unsigned int p;
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for (i=0; i<ARRAY_SIZE(spi_pinmux_config); i++) {
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pin = hal_gpio_name2pin(spi_pinmux_config[i].name);
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if (pin < 0)
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continue;
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g = GPIO_GROUP(pin);
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p = GPIO_GROUP_PIN(pin);
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hal_gpio_set_func(g, p, spi_pinmux_config[i].func);
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hal_gpio_set_bias_pull(g, p, spi_pinmux_config[i].bias);
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hal_gpio_set_drive_strength(g, p, spi_pinmux_config[i].drive);
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}
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}
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static irqreturn_t qspi_slave_irq_handler(int irq_num, void *arg)
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{
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qspi_slave_handle *h = arg;
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rt_interrupt_enter();
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hal_qspi_slave_irq_handler(h);
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rt_interrupt_leave();
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return IRQ_HANDLED;
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}
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int test_qspi_slave_controller_init(u32 id, u32 bus_width,
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qspi_slave_async_cb cb, void *priv,
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qspi_slave_handle *h)
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{
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struct qspi_slave_config cfg;
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int ret;
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u32 clk_id, irq_num, clk_in;
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clk_id = qspi_clk_ids[id];
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irq_num = qspi_irq_num[id];
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clk_in = qspi_input_clk[id];
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memset(&cfg, 0, sizeof(cfg));
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cfg.idx = id;
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cfg.clk_in_hz = clk_in;
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cfg.clk_id = clk_id;
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/* Default is Mode0 */
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cfg.cpol = HAL_QSPI_CPOL_ACTIVE_HIGH;
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cfg.cpha = HAL_QSPI_CPHA_FIRST_EDGE;
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cfg.cs_polarity = HAL_QSPI_CS_POL_VALID_LOW;
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ret = hal_qspi_slave_init(h, &cfg);
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if (ret) {
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pr_err("hal_qspi_slave_init failed. ret %d\n", ret);
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return -1;
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}
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hal_qspi_slave_set_bus_width(h, bus_width);
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ret = hal_qspi_slave_register_cb(h, cb, priv);
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if (ret) {
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pr_err("qspi register async callback failed.\n");
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return ret;
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}
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aicos_request_irq(irq_num, qspi_slave_irq_handler, 0, NULL, (void *)h);
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aicos_irq_enable(irq_num);
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return 0;
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}
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void test_qspi_slave_controller_deinit(qspi_slave_handle *h)
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{
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hal_qspi_slave_deinit(h);
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}
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