v1.1.2:add audio and efuse patch

bsp/Kconfig

@@ -451,6 +451,24 @@ config AIC_SID_BARE_TEST
     default n
     depends on AIC_SID_DRV
 
+config AIC_SID_BURN_SPIENC_KEY_TEST
+    bool "Enable SID burn spienc key command"
+    default n
+    depends on AIC_SID_DRV
+    depends on EFUSE_WRITE_SUPPORT
+    depends on DRIVER_BARE_DRV_EN
+
+if AIC_SID_BURN_SPIENC_KEY_TEST
+
+    config AIC_SID_BURN_SIMULATED
+        bool "Enable SID simulated burning"
+        default n
+
+    config AIC_SID_CONTINUE_BOOT_BURN_AFTER
+        bool "Enable SID continue to boot after burning"
+        default n
+endif
+
 config AIC_DM_LIB_TEST
     bool "Enable DM Lib test command"
     default n

bsp/artinchip/drv/efuse/Kconfig.dev

@@ -4,14 +4,20 @@
 menu "SID Parameter"
     depends on AIC_USING_SID
 
+    config EFUSE_WRITE_SUPPORT
+	bool "support efuse write"
+	default n
+
     config EFUSE_MAX_WORD
 	int "set efuse max word"
-	default 64
+	default 16 if AIC_CHIP_D12X
+	default 64 if AIC_CHIP_D21X || AIC_CHIP_D13X || AIC_CHIP_G73X
 
     config EFUSE_TIMING_VALUE
 	hex "set timing value"
 	default 0x0402FFD8 if AIC_CHIP_D21X
 	default 0x0402FFD8 if AIC_CHIP_D13X || AIC_CHIP_G73X
 	default 0x04021FF1 if AIC_CHIP_D12X
+	default 0x04021FF1 if AIC_CHIP_AIC1606SE
 endmenu
 

bsp/artinchip/drv/efuse/drv_efuse.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
+ * Copyright (c) 2022-2025, ArtInChip Technology Co., Ltd
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -26,13 +26,28 @@ static int drv_efuse_init(void)
     return RT_TRUE;
 }
 
+void drv_efuse_write_enable(void)
+{
+    hal_efuse_write_enable();
+}
+
+void drv_efuse_write_disable(void)
+{
+    hal_efuse_write_disable();
+}
+
 int drv_efuse_read(u32 addr, void *data, u32 size)
 {
     u32 wid, wval, rest, cnt;
     u8 *pd, *pw;
     int ret;
 
+    if (hal_efuse_clk_enable()) {
+        return RT_FALSE;
+    }
+
     if (hal_efuse_wait_ready()) {
+        hal_efuse_clk_disable();
         LOG_E("eFuse is not ready.\n");
         return RT_FALSE;
     }
@@ -60,6 +75,8 @@ int drv_efuse_read(u32 addr, void *data, u32 size)
         rest -= cnt;
     }
 
+    hal_efuse_clk_disable();
+
     return (int)(size - rest);
 }
 
@@ -125,6 +142,7 @@ int drv_efuse_read_reserved_2(void *data)
     return 0;
 }
 
+#ifdef EFUSE_WRITE_SUPPORT
 int drv_efuse_program(u32 addr, const void *data, u32 size)
 {
     u32 wid, wval, rest, cnt;
@@ -132,7 +150,12 @@ int drv_efuse_program(u32 addr, const void *data, u32 size)
     u8 *pw;
     int ret;
 
+    if (hal_efuse_clk_enable()) {
+        return RT_FALSE;
+    }
+
     if (hal_efuse_wait_ready()) {
+        hal_efuse_clk_disable();
         LOG_E("eFuse is not ready.\n");
         return RT_FALSE;
     }
@@ -162,17 +185,40 @@ int drv_efuse_program(u32 addr, const void *data, u32 size)
         rest -= cnt;
     }
 
+    hal_efuse_clk_disable();
+
     return (int)(size - rest);
 }
+#endif
 
 int drv_sjtag_auth(u32 *key, u32 kwlen)
 {
-    return hal_sjtag_auth(key, kwlen);
+    int ret;
+
+    if (hal_efuse_clk_enable()) {
+        return RT_FALSE;
+    }
+
+    ret = hal_sjtag_auth(key, kwlen);
+
+    hal_efuse_clk_disable();
+
+    return ret;
 }
 
 int drv_szone_auth(u32 *key, u32 kwlen)
 {
-    return hal_szone_auth(key, kwlen);
+    int ret;
+
+    if (hal_efuse_clk_enable()) {
+        return RT_FALSE;
+    }
+
+    ret = hal_szone_auth(key, kwlen);
+
+    hal_efuse_clk_disable();
+
+    return ret;
 }
 
 INIT_DEVICE_EXPORT(drv_efuse_init);

bsp/artinchip/drv/efuse/efuse_cmds.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
+ * Copyright (c) 2022-2025, ArtInChip Technology Co., Ltd
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,9 +16,11 @@ static void cmd_efuse_help(void)
     printf("  efuse help                     : Get this help.\n");
     printf("  efuse dump     offset len      : Dump data from eFuse offset.\n");
     printf("  efuse read     addr offset len : Read eFuse data to RAM addr.\n");
+#ifdef EFUSE_WRITE_SUPPORT
     printf("  efuse write    addr offset len : Write data to eFuse from RAM addr.\n");
     printf("  efuse writehex offset data     : Write data to eFuse from input hex string.\n");
     printf("  efuse writestr offset data     : Write data to eFuse from input string.\n");
+#endif
     printf("  efuse authenticate sjtag key   : Authenticate secure jtag from hex string key.\n");
     printf("  efuse authenticate szone key   : Authenticate secure zone from hex string key.\n");
 }
@@ -80,6 +82,7 @@ static void cmd_efuse_dump(int argc, char **argv)
     printf("\n");
 }
 
+#ifdef EFUSE_WRITE_SUPPORT
 static void cmd_efuse_write(int argc, char **argv)
 {
     ulong addr, offset, len;
@@ -155,6 +158,7 @@ static void cmd_efuse_writestr(int argc, char **argv)
 
     printf("Program efuse done.\n");
 }
+#endif
 
 static void cmd_efuse_authenticate(int argc, char **argv)
 {
@@ -203,18 +207,26 @@ static void cmd_efuse_do(int argc, char **argv)
         cmd_efuse_dump(argc - 1, &argv[1]);
         return;
     }
+#ifdef EFUSE_WRITE_SUPPORT
     if (!strcmp(argv[1], "write")) {
+        drv_efuse_write_enable();
         cmd_efuse_write(argc - 1, &argv[1]);
+        drv_efuse_write_disable();
         return;
     }
     if (!strcmp(argv[1], "writehex")) {
+        drv_efuse_write_enable();
         cmd_efuse_writehex(argc - 1, &argv[1]);
+        drv_efuse_write_disable();
         return;
     }
     if (!strcmp(argv[1], "writestr")) {
+        drv_efuse_write_enable();
         cmd_efuse_writestr(argc - 1, &argv[1]);
+        drv_efuse_write_disable();
         return;
     }
+#endif
     if (!strcmp(argv[1], "authenticate")) {
         cmd_efuse_authenticate(argc - 1, &argv[1]);
         return;

bsp/artinchip/drv_bare/efuse/efuse.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
+ * Copyright (c) 2022-2025, ArtInChip Technology Co., Ltd
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -24,13 +24,28 @@ int efuse_init(void)
     return 0;
 }
 
+void efuse_write_enable(void)
+{
+    hal_efuse_write_enable();
+}
+
+void efuse_write_disable(void)
+{
+    hal_efuse_write_disable();
+}
+
 int efuse_read(u32 addr, void *data, u32 size)
 {
     u32 wid, wval, rest, cnt;
     u8 *pd, *pw;
     int ret;
 
+    if (hal_efuse_clk_enable()) {
+        return -1;
+    }
+
     if (hal_efuse_wait_ready()) {
+        hal_efuse_clk_disable();
         pr_err("eFuse is not ready.\n");
         return -1;
     }
@@ -58,6 +73,8 @@ int efuse_read(u32 addr, void *data, u32 size)
         rest -= cnt;
     }
 
+    hal_efuse_clk_disable();
+
     return (int)(size - rest);
 }
 
@@ -82,6 +99,7 @@ int efuse_read_chip_id(void *data)
     return 0;
 }
 
+#ifdef EFUSE_WRITE_SUPPORT
 int efuse_program(u32 addr, const void *data, u32 size)
 {
     u32 wid, wval, rest, cnt;
@@ -89,7 +107,12 @@ int efuse_program(u32 addr, const void *data, u32 size)
     u8 *pw;
     int ret;
 
+    if (hal_efuse_clk_enable()) {
+        return -1;
+    }
+
     if (hal_efuse_wait_ready()) {
+        hal_efuse_clk_disable();
         pr_err("eFuse is not ready.\n");
         return -1;
     }
@@ -119,15 +142,38 @@ int efuse_program(u32 addr, const void *data, u32 size)
         rest -= cnt;
     }
 
+    hal_efuse_clk_disable();
+
     return (int)(size - rest);
 }
+#endif
 
 int sjtag_auth(u32 *key, u32 kwlen)
 {
-    return hal_sjtag_auth(key, kwlen);
+    int ret;
+
+    if (hal_efuse_clk_enable()) {
+        return -1;
+    }
+
+    ret = hal_sjtag_auth(key, kwlen);
+
+    hal_efuse_clk_disable();
+
+    return ret;
 }
 
 int szone_auth(u32 *key, u32 kwlen)
 {
-    return hal_szone_auth(key, kwlen);
+    int ret;
+
+    if (hal_efuse_clk_enable()) {
+        return -1;
+    }
+
+    ret = hal_szone_auth(key, kwlen);
+
+    hal_efuse_clk_disable();
+
+    return ret;
 }

bsp/artinchip/hal/efuse/hal_efuse.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
+ * Copyright (c) 2022-2025, ArtInChip Technology Co., Ltd
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -43,7 +43,19 @@
 #define EFUSE_STS_WRITING      3
 #define EFUSE_STS_READING      4
 
+static u32 opcode = 0;
+
 int hal_efuse_init(void)
+{
+    return 0;
+}
+
+int hal_efuse_deinit(void)
+{
+    return 0;
+}
+
+int hal_efuse_clk_enable(void)
 {
     int ret = 0, val = EFUSE_TIMING_VALUE;
 
@@ -64,7 +76,7 @@ int hal_efuse_init(void)
     return 0;
 }
 
-int hal_efuse_deinit(void)
+int hal_efuse_clk_disable(void)
 {
     hal_clk_disable_assertrst(CLK_SID);
     hal_clk_disable(CLK_SID);
@@ -72,6 +84,16 @@ int hal_efuse_deinit(void)
     return 0;
 }
 
+void hal_efuse_write_enable(void)
+{
+    opcode = EFUSE_OP_CODE;
+}
+
+void hal_efuse_write_disable(void)
+{
+    opcode = 0;
+}
+
 int hal_efuse_get_version(void)
 {
     return readl(EFUSE_REG_VER);
@@ -126,6 +148,7 @@ int hal_efuse_read(u32 wid, u32 *wval)
     return 0;
 }
 
+#ifdef EFUSE_WRITE_SUPPORT
 int hal_efuse_write(u32 wid, u32 wval)
 {
     u32 addr, val, i;
@@ -134,7 +157,7 @@ int hal_efuse_write(u32 wid, u32 wval)
         hal_log_err("Error, word id is too large.\n");
         return -EINVAL;
     }
-    
+
     for (i = 0; i < 2; i++) {
         addr = (wid + EFUSE_MAX_WORD * i) << 2;
         writel(addr, EFUSE_REG_ADDR);
@@ -146,7 +169,7 @@ int hal_efuse_write(u32 wid, u32 wval)
         */
         val = readl(EFUSE_REG_CTL);
         val &= ~((0xFFF << 16) | (1 << 0));
-        val |= ((EFUSE_OP_CODE << 16) | (1 << 0));
+        val |= ((opcode << 16) | (1 << 0));
         writel(val, EFUSE_REG_CTL);
 
         /* Wait write finish */
@@ -157,6 +180,7 @@ int hal_efuse_write(u32 wid, u32 wval)
 
     return 0;
 }
+#endif
 
 int hal_write_auth_key(u32 *key, u32 kwlen)
 {

bsp/artinchip/hal/mac/aicmac_macaddr.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
+ * Copyright (c) 2022-2025, ArtInChip Technology Co., Ltd
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -9,7 +9,12 @@
 #include "aic_log.h"
 #include <string.h>
 
-#define AICMAC_CHIPID_LENGTH    6
+#include <stdio.h>
+#include <stdint.h>
+#include <string.h>
+
+#include "md5.h"
+#define AICMAC_CHIPID_LENGTH    8
 
 
 static int aicmac_efuse_read(u32 addr, void *data, u32 size)
@@ -18,6 +23,10 @@ static int aicmac_efuse_read(u32 addr, void *data, u32 size)
     u8 *pd, *pw;
     int ret;
 
+    if (hal_efuse_clk_enable()) {
+        return -1;
+    }
+
     if (hal_efuse_wait_ready()) {
         pr_err("eFuse is not ready.\n");
         return -1;
@@ -46,6 +55,8 @@ static int aicmac_efuse_read(u32 addr, void *data, u32 size)
         rest -= cnt;
     }
 
+    hal_efuse_clk_disable();
+
     return (int)(size - rest);
 }
 
@@ -56,22 +67,29 @@ static inline int aicmac_get_chipid(unsigned char out_chipid[AICMAC_CHIPID_LENGT
 
 void aicmac_get_macaddr_from_chipid(int port, unsigned char out_addr[6])
 {
-    unsigned char chipid[AICMAC_CHIPID_LENGTH];
+    unsigned char hex_chipid[AICMAC_CHIPID_LENGTH] = { 0 };
-    unsigned char key[AICMAC_CHIPID_LENGTH] = {'a', 'i', 'c', 'k', 'e', 'y'};
+    char char_chipid[AICMAC_CHIPID_LENGTH * 2 + 1] = { 0 };
+    uint8_t md5_ahash[16] = { 0 };
     int i;
 
-    if (!aicmac_get_chipid(chipid))
+    if (!aicmac_get_chipid(hex_chipid))
         return;
 
-    for (i = 0; i < AICMAC_CHIPID_LENGTH; i++) {
+    for (i = 0; i < AICMAC_CHIPID_LENGTH ; i++) {
-        out_addr[AICMAC_CHIPID_LENGTH - 1 - i] = chipid[i] ^ key[i];
+        sprintf(&char_chipid[i * 2], "%02X", hex_chipid[i]);
     }
 
     if (port)
-        out_addr[1] ^= 0x55;
+        char_chipid[15] = 'a';
     else
-        out_addr[1] ^= 0xAA;
+        char_chipid[15] = 'A';
 
-    out_addr[0] &= 0xFE;
+    MD5Buffer(char_chipid, 16, md5_ahash);
-    out_addr[0] |= 0x02;
+
+    /* Choose md5 result's [0][2][4][6][8][10] byte as mac address */
+    for (i = 0; i < 6; i++)
+        out_addr[i] = md5_ahash[2 * i];
+
+    out_addr[0] &= 0xfe; /* clear multicast bit */
+    out_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */
 }

bsp/artinchip/hal/syscfg/syscfg_hw_v1.1.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024, ArtInChip Technology Co., Ltd
+ * Copyright (c) 2024-2025, ArtInChip Technology Co., Ltd
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -248,7 +248,9 @@ static inline void syscfg_hw_sip_flash_init(void)
 #if defined(AIC_USING_SID)
 u32 map;
     /* 1. Read eFuse to set SiP flash IO mapping */
+    hal_efuse_clk_enable();
     hal_efuse_read(IOMAP_EFUSE_WID, &val);
+    hal_efuse_clk_disable();
     map = (val >> EFUSE_DATA_IOMAP_POS) & 0xFF;
 
     /* 2. Set the SiP flash's access Controller */

bsp/artinchip/hal/syscfg/syscfg_hw_v1.2.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024, ArtInChip Technology Co., Ltd
+ * Copyright (c) 2024-2025, ArtInChip Technology Co., Ltd
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -175,7 +175,9 @@ static inline void syscfg_hw_sip_flash_init(void)
 #if defined(AIC_USING_SID)
 u32 map;
     /* 1. Read eFuse to set SiP flash IO mapping */
+    hal_efuse_clk_enable();
     hal_efuse_read(IOMAP_EFUSE_WID, &val);
+    hal_efuse_clk_disable();
     map = (val >> EFUSE_DATA_IOMAP_POS) & 0xFF;
 
     /* 2. Set the SiP flash's access Controller */

bsp/artinchip/hal/tsen/hal_tsen.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
+ * Copyright (c) 2022-2025, ArtInChip Technology Co., Ltd
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -233,6 +233,10 @@ int hal_tsen_efuse_read(u32 addr, u32 *data, u32 size)
     int ret;
     int length = TSEN_EFUSE_STANDARD_LENGTH;
 
+    if (hal_efuse_clk_enable()) {
+        return -1;
+    }
+
     rest = size;
     while (rest > 0) {
         wid = addr >> 2;
@@ -252,6 +256,8 @@ int hal_tsen_efuse_read(u32 addr, u32 *data, u32 size)
         rest -= cnt;
     }
 
+    hal_efuse_clk_disable();
+
     return (int)(size - rest);
 }
 #endif

bsp/artinchip/include/drv/drv_efuse.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
+ * Copyright (c) 2022-2025, ArtInChip Technology Co., Ltd
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -15,6 +15,8 @@ extern "C" {
 
 #include <aic_core.h>
 
+void drv_efuse_write_enable(void);
+void drv_efuse_write_disable(void);
 int drv_efuse_read(u32 addr, void *data, u32 size);
 int drv_efuse_read_chip_id(void *data);
 int drv_efuse_read_reserved_1(void *data);

bsp/artinchip/include/drv_bare/efuse.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
+ * Copyright (c) 2022-2025, ArtInChip Technology Co., Ltd
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,6 +16,8 @@ extern "C" {
 #include <aic_core.h>
 
 int efuse_init(void);
+void efuse_write_enable(void);
+void efuse_write_disable(void);
 int efuse_read(u32 addr, void *data, u32 size);
 int efuse_read_chip_id(void *data);
 int efuse_program(u32 addr, const void *data, u32 size);

bsp/artinchip/include/hal/hal_efuse.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
+ * Copyright (c) 2022-2025, ArtInChip Technology Co., Ltd
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,6 +17,10 @@ extern "C" {
 
 int hal_efuse_init(void);
 int hal_efuse_deinit(void);
+int hal_efuse_clk_enable(void);
+int hal_efuse_clk_disable(void);
+void hal_efuse_write_enable(void);
+void hal_efuse_write_disable(void);
 int hal_efuse_get_version(void);
 int hal_efuse_wait_ready(void);
 int hal_efuse_read(u32 wid, u32 *wval);

bsp/artinchip/sys/d12x/ram_param.c

@@ -1,5 +1,8 @@
 /*
- * Copyright (C) 2024 ArtInChip Technology Co.,Ltd
+ * Copyright (C) 2024-2025 ArtInChip Technology Co.,Ltd
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
  * Author: Xiong Hao <hao.xiong@artinchip.com>
  */
 
@@ -8,6 +11,10 @@
 #include <aic_common.h>
 #include <ram_param.h>
 
+#define EFUSE_CMU_REG ((void *)0x18020904)
+#define EFUSE_218_REG ((void *)0x19010218)
+#define EFUSE_21C_REG ((void *)0x1901021c)
+
 #define PSRAM_SINGLE   0
 #define PSRAM_PARALLEL 1
 
@@ -42,20 +49,26 @@ struct _psram_info {
     /* D121BBV 8M */                                                            \
     {0x04, PSRAM_PARALLEL, 0x800000, {APS3208K, 0x80c980c9}},                   \
     /* D122BCV1 16M SCKW18X128160AAE1 */                                        \
-    {0x05, PSRAM_PARALLEL, 0x1000000, {SCKW18_12816O, 0xc59ac59a}},  \
+    {0x05, PSRAM_PARALLEL, 0x1000000, {SCKW18_12816O, 0xc59ac59a}},             \
     /* D122BCV2 16M AP12816 */                                                  \
-    {0x05, PSRAM_PARALLEL, 0x1000000, {APS12816O, 0xdd8ddd8d}},      \
+    {0x05, PSRAM_PARALLEL, 0x1000000, {APS12816O, 0xdd8ddd8d}},                 \
+    /* D123BAV 4M */                                                            \
+    {0x07, PSRAM_SINGLE, 0x400000, {APS3208K, 0x80c980c9}},          \
+    /* D123BBV 8M */                                                            \
+    {0x08, PSRAM_PARALLEL, 0x800000, {APS3208K, 0x80c980c9}},        \
+    /* D123BCV 16M */                                                           \
+    {0x09, PSRAM_PARALLEL, 0x1000000, {APS12816O, 0xdd8ddd8d}},      \
     /* TR230 8M */                                                              \
-    {0xA1, PSRAM_PARALLEL, 0x800000, {APS3208K, 0x80c980c9}},        \
+    {0xA1, PSRAM_PARALLEL, 0x800000, {APS3208K, 0x80c980c9}},                   \
     /* JYX58 8M */                                                              \
-    {0xB1, PSRAM_PARALLEL, 0x800000, {APS3208K, 0x80c980c9}},        \
+    {0xB1, PSRAM_PARALLEL, 0x800000, {APS3208K, 0x80c980c9}},                   \
 }
 
 struct _psram_info psram_table_info[] = PSRAM_TABLE_INFO;
 
 u8 psram_get_mark_id(void)
 {
-    u32 fuse_218 = readl(0x19010218);
+    u32 fuse_218 = readl(EFUSE_218_REG);
     u8 mark_id = fuse_218 & 0xff;
 
     pr_info("fuse_218(0x19010218)=0x%x, mark_id=0x%x\n", fuse_218, mark_id);
@@ -64,7 +77,7 @@ u8 psram_get_mark_id(void)
 
 u8 psram_get_psram_id(void)
 {
-    u32 fuse_21c = readl(0x1901021c);
+    u32 fuse_21c = readl(EFUSE_21C_REG);
     u8 psram_id = (fuse_21c & 0xff) >> 4;
 
     pr_info("fuse_21c(0x1901021c)=0x%x, psram_id=0x%x\n", fuse_21c, psram_id);
@@ -90,9 +103,11 @@ u32 aic_get_ram_size(void)
     struct _psram_info *psram_info;
     u8 mark_id, psram_id;
 
+    writel(0x1100, EFUSE_CMU_REG);
     mark_id = psram_get_mark_id();
     psram_id = psram_get_psram_id();
     psram_info = psram_get_info(mark_id, psram_id);
+    writel(0x0, EFUSE_CMU_REG);
 
     return psram_info->psram_size;
 }

bsp/artinchip/sys/d13x/ram_param.c

@@ -1,5 +1,8 @@
 /*
- * Copyright (C) 2024 ArtInChip Technology Co.,Ltd
+ * Copyright (C) 2024-2025 ArtInChip Technology Co.,Ltd
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
  * Author: Xiong Hao <hao.xiong@artinchip.com>
  */
 
@@ -8,6 +11,10 @@
 #include <aic_common.h>
 #include <ram_param.h>
 
+#define EFUSE_CMU_REG ((void *)0x18020904)
+#define EFUSE_218_REG ((void *)0x19010218)
+#define EFUSE_224_REG ((void *)0x19010224)
+
 #define PSRAM_SINGLE   0
 #define PSRAM_PARALLEL 1
 
@@ -65,7 +72,7 @@ struct _psram_info psram_table_info[] = PSRAM_TABLE_INFO;
 
 u8 psram_get_mark_id(void)
 {
-    u32 fuse_218 = readl(0x19010218);
+    u32 fuse_218 = readl(EFUSE_218_REG);
     u8 mark_id = fuse_218 & 0xff;
 
     pr_info("fuse_218(0x19010218)=0x%x, mark_id=0x%x\n", fuse_218, mark_id);
@@ -74,7 +81,7 @@ u8 psram_get_mark_id(void)
 
 u8 psram_get_psram_id(void)
 {
-    u32 fuse_224 = readl(0x19010224);
+    u32 fuse_224 = readl(EFUSE_224_REG);
     u8 psram_id = (fuse_224 & 0xff0000) >> 20;
 
     pr_info("fuse_224(0x19010224)=0x%x, psram_id=0x%x\n", fuse_224, psram_id);
@@ -100,9 +107,11 @@ u32 aic_get_ram_size(void)
     struct _psram_info *psram_info;
     u8 mark_id, psram_id;
 
+    writel(0x1100, EFUSE_CMU_REG);
     mark_id = psram_get_mark_id();
     psram_id = psram_get_psram_id();
     psram_info = psram_get_info(mark_id, psram_id);
+    writel(0x0, EFUSE_CMU_REG);
 
     return psram_info->psram_size;
 }

bsp/artinchip/sys/d21x/ram_param.c

@@ -1,5 +1,8 @@
 /*
- * Copyright (C) 2024 ArtInChip Technology Co.,Ltd
+ * Copyright (C) 2024-2025 ArtInChip Technology Co.,Ltd
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
  * Author: Xiong Hao <hao.xiong@artinchip.com>
  */
 
@@ -43,6 +46,7 @@ static u32 efuse_get_ddr_size(void)
         default:
             pr_info("No DDR info\n");
     }
+    writel(0x0, EFUSE_CMU_REG);
 
     return size;
 }

bsp/artinchip/sys/g73x/ram_param.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2024 ArtInChip Technology Co.,Ltd
+ * Copyright (C) 2024-2025 ArtInChip Technology Co.,Ltd
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -11,6 +11,10 @@
 #include <aic_common.h>
 #include <ram_param.h>
 
+#define EFUSE_CMU_REG ((void *)0x18020904)
+#define EFUSE_218_REG ((void *)0x19010218)
+#define EFUSE_224_REG ((void *)0x19010224)
+
 #define PSRAM_SINGLE   0
 #define PSRAM_PARALLEL 1
 
@@ -48,7 +52,7 @@ struct _psram_info psram_table_info[] = PSRAM_TABLE_INFO;
 
 u8 psram_get_mark_id(void)
 {
-    u32 fuse_218 = readl(0x19010218);
+    u32 fuse_218 = readl(EFUSE_218_REG);
     u8 mark_id = fuse_218 & 0xff;
 
     pr_info("fuse_218(0x19010218)=0x%x, mark_id=0x%x\n", fuse_218, mark_id);
@@ -57,7 +61,7 @@ u8 psram_get_mark_id(void)
 
 u8 psram_get_psram_id(void)
 {
-    u32 fuse_224 = readl(0x19010224);
+    u32 fuse_224 = readl(EFUSE_224_REG);
     u8 psram_id = (fuse_224 & 0xff0000) >> 20;
 
     pr_info("fuse_224(0x19010224)=0x%x, psram_id=0x%x\n", fuse_224, psram_id);
@@ -83,9 +87,11 @@ u32 aic_get_ram_size(void)
     struct _psram_info *psram_info;
     u8 mark_id, psram_id;
 
+    writel(0x1100, EFUSE_CMU_REG);
     mark_id = psram_get_mark_id();
     psram_id = psram_get_psram_id();
     psram_info = psram_get_info(mark_id, psram_id);
+    writel(0x0, EFUSE_CMU_REG);
 
     return psram_info->psram_size;
 }

bsp/examples_bare/test-efuse/SConscript

@@ -7,7 +7,10 @@ CPPPATH = []
 src = []
 
 if GetDepend('KERNEL_BAREMETAL') and GetDepend('AIC_SID_BARE_TEST'):
-    src += Glob('*.c')
+    src += Glob('efuse_cmds.c')
+
+if GetDepend('KERNEL_BAREMETAL') and GetDepend('AIC_SID_BURN_SPIENC_KEY_TEST'):
+    src += Glob('efuse_burn_spienc_key_cmd.c')
 
 group = DefineGroup('test-efuse', src, depend = [''], CPPPATH = CPPPATH)
 

bsp/examples_bare/test-efuse/efuse_burn_spienc_key_cmd.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
+ * Copyright (c) 2022-2025, ArtInChip Technology Co., Ltd
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -14,18 +14,9 @@
 #include <aic_utils.h>
 #include "spi_aes_key.h"
 
-// #define D12X_BURN_SPIENC_KEY_ENABLE
-// #define D13X_BURN_SPIENC_KEY_ENABLE
-// #define DRY_RUN_TO_CONFIRM_KEY_VAL
-// Enable one of the above as required
-
-/* The eFuse size */
-#define D12X_EFUSE_SIZE (512 / 8)
-#define D13X_EFUSE_SIZE (2048 / 8)
-
 int write_efuse(char *msg, u32 offset, const void *val, u32 size)
 {
-#if defined(DRY_RUN_TO_CONFIRM_KEY_VAL)
+#if defined(AIC_SID_BURN_SIMULATED)
     printf("eFuse %s:\n", msg);
     hexdump((unsigned char *)val, size, 1);
     return size;
@@ -39,11 +30,11 @@ int burn_brom_spienc_bit(void)
     u32 offset = 0xFFFF, val;
     int ret;
 
-#if defined(D12X_BURN_SPIENC_KEY_ENABLE)
+#if defined(AIC_CHIP_D12X)
     offset = 0x4;
     val = 0;
     val |= (1 << 28); // SPIENC boot bit for brom
-#elif defined(D13X_BURN_SPIENC_KEY_ENABLE)
+#elif defined(AIC_CHIP_D13X) || defined(AIC_CHIP_D21X) || defined(AIC_CHIP_G73X)
     offset = 0x38;
     val = 0;
     val |= (1 << 16); // Secure boot bit for brom
@@ -63,11 +54,11 @@ int check_brom_spienc_bit(void)
     u32 offset = 0xFFFF, val, mskval = 0;
     int ret;
 
-#if defined(D12X_BURN_SPIENC_KEY_ENABLE)
+#if defined(AIC_CHIP_D12X)
     offset = 4;
     mskval = 0;
     mskval |= (1 << 28); // SPIENC boot bit for brom
-#elif defined(D13X_BURN_SPIENC_KEY_ENABLE)
+#elif defined(AIC_CHIP_D13X) || defined(AIC_CHIP_D21X) || defined(AIC_CHIP_G73X)
     offset = 0x38;
     mskval = 0;
     mskval |= (1 << 16); // Secure boot bit for brom
@@ -92,11 +83,11 @@ int burn_jtag_lock_bit(void)
     u32 offset = 0xFFFF, val;
     int ret;
 
-#if defined(D12X_BURN_SPIENC_KEY_ENABLE)
+#if defined(AIC_CHIP_D12X)
     offset = 4;
     val = 0;
     val |= (1 << 24); // JTAG LOCK
-#elif defined(D13X_BURN_SPIENC_KEY_ENABLE)
+#elif defined(AIC_CHIP_D13X) || defined(AIC_CHIP_D21X) || defined(AIC_CHIP_G73X)
     offset = 0x38;
     val = 0;
     val |= (1 << 0); // JTAG LOCK
@@ -115,11 +106,11 @@ int check_jtag_lock_bit(void)
     u32 offset = 0xFFFF, val, mskval = 0;
     int ret;
 
-#if defined(D12X_BURN_SPIENC_KEY_ENABLE)
+#if defined(AIC_CHIP_D12X)
     offset = 4;
     mskval = 0;
     mskval |= (1 << 24); // JTAG LOCK
-#elif defined(D13X_BURN_SPIENC_KEY_ENABLE)
+#elif defined(AIC_CHIP_D13X) || defined(AIC_CHIP_D21X) || defined(AIC_CHIP_G73X)
     offset = 0x38;
     mskval = 0;
     mskval |= (1 << 0); // JTAG LOCK
@@ -143,9 +134,9 @@ int burn_spienc_key(void)
     u32 offset = 0xFFFF;
     int ret;
 
-#if defined(D12X_BURN_SPIENC_KEY_ENABLE)
+#if defined(AIC_CHIP_D12X)
     offset = 0x20;
-#elif defined(D13X_BURN_SPIENC_KEY_ENABLE)
+#elif defined(AIC_CHIP_D13X) || defined(AIC_CHIP_D21X) || defined(AIC_CHIP_G73X)
     offset = 0xA0;
 #endif
     ret = write_efuse("spi_aes.key", offset, (const void *)spi_aes_key, spi_aes_key_len);
@@ -163,9 +154,9 @@ int check_spienc_key(void)
     u8 data[256];
     int ret;
 
-#if defined(D12X_BURN_SPIENC_KEY_ENABLE)
+#if defined(AIC_CHIP_D12X)
     offset = 0x20;
-#elif defined(D13X_BURN_SPIENC_KEY_ENABLE)
+#elif defined(AIC_CHIP_D13X) || defined(AIC_CHIP_D21X) || defined(AIC_CHIP_G73X)
     offset = 0xA0;
 #endif
     ret = efuse_read(offset, (void *)data, 16);
@@ -181,7 +172,7 @@ int check_spienc_key(void)
 
 int burn_spienc_nonce(void)
 {
-#ifdef D13X_BURN_SPIENC_KEY_ENABLE
+#if defined(AIC_CHIP_D13X) || defined(AIC_CHIP_D21X) || defined(AIC_CHIP_G73X)
     u32 offset;
     int ret;
 
@@ -197,7 +188,7 @@ int burn_spienc_nonce(void)
 
 int check_spienc_nonce(void)
 {
-#ifdef D13X_BURN_SPIENC_KEY_ENABLE
+#if defined(AIC_CHIP_D13X) || defined(AIC_CHIP_D21X) || defined(AIC_CHIP_G73X)
     u32 offset;
     u8 data[256];
     int ret;
@@ -215,13 +206,13 @@ int check_spienc_nonce(void)
     return 0;
 }
 
-#if defined(D13X_BURN_SPIENC_KEY_ENABLE)
+#if defined(AIC_CHIP_D13X) || defined(AIC_CHIP_D21X) || defined(AIC_CHIP_G73X)
 int burn_spienc_rotpk(void)
 {
     u32 offset = 0xFFFF;
     int ret;
 
-#if defined(D13X_BURN_SPIENC_KEY_ENABLE)
+#if defined(AIC_CHIP_D13X) || defined(AIC_CHIP_D21X) || defined(AIC_CHIP_G73X)
     offset = 0x40;
 #endif
     ret = write_efuse("rotpk.bin", offset, (const void *)rotpk_bin, rotpk_bin_len);
@@ -239,7 +230,7 @@ int check_spienc_rotpk(void)
     u8 data[256];
     int ret;
 
-#if defined(D13X_BURN_SPIENC_KEY_ENABLE)
+#if defined(AIC_CHIP_D13X) || defined(AIC_CHIP_D21X) || defined(AIC_CHIP_G73X)
     offset = 0x40;
 #endif
     ret = efuse_read(offset, (void *)data, 16);
@@ -256,7 +247,7 @@ int check_spienc_rotpk(void)
 
 int burn_spienc_key_read_write_disable_bits(void)
 {
-#if defined(D12X_BURN_SPIENC_KEY_ENABLE)
+#if defined(AIC_CHIP_D12X)
     u32 offset, val;
     int ret;
 
@@ -268,7 +259,7 @@ int burn_spienc_key_read_write_disable_bits(void)
         printf("Write r/w disable bit efuse error.\n");
         return -1;
     }
-#elif defined(D13X_BURN_SPIENC_KEY_ENABLE)
+#elif defined(AIC_CHIP_D13X) || defined(AIC_CHIP_D21X) || defined(AIC_CHIP_G73X)
     u32 offset, val;
     int ret;
 
@@ -308,7 +299,7 @@ int burn_spienc_key_read_write_disable_bits(void)
 
 int check_spienc_key_read_write_disable_bits(void)
 {
-#if defined(D12X_BURN_SPIENC_KEY_ENABLE)
+#if defined(AIC_CHIP_D12X)
     u32 offset, val, mskval;
     int ret;
 
@@ -328,7 +319,7 @@ int check_spienc_key_read_write_disable_bits(void)
         printf("SPI ENC Key is write DISABLED\n");
     else
         printf("SPI ENC Key is NOT write disabled\n");
-#elif defined(D13X_BURN_SPIENC_KEY_ENABLE)
+#elif defined(AIC_CHIP_D13X) || defined(AIC_CHIP_D21X) || defined(AIC_CHIP_G73X)
     u32 offset, val, mskval;
     int ret;
 
@@ -381,29 +372,34 @@ int cmd_efuse_do_spienc(int argc, char **argv)
     int ret;
 
     efuse_init();
+    efuse_write_enable();
 
-#if defined(D12X_BURN_SPIENC_KEY_ENABLE) || defined(D13X_BURN_SPIENC_KEY_ENABLE)
+#if defined(AIC_CHIP_D12X) || defined(AIC_CHIP_D13X) || defined(AIC_CHIP_D21X) || defined(AIC_CHIP_G73X)
     ret = burn_brom_spienc_bit();
     if (ret) {
+        efuse_write_disable();
         printf("Error\n");
         return -1;
     }
 
     ret = burn_spienc_key();
     if (ret) {
+        efuse_write_disable();
         printf("Error\n");
         return -1;
     }
 
     ret = burn_spienc_nonce();
     if (ret) {
+        efuse_write_disable();
         printf("Error\n");
         return -1;
     }
 
-#if defined(D13X_BURN_SPIENC_KEY_ENABLE)
+#if defined(AIC_CHIP_D13X) || defined(AIC_CHIP_D21X) || defined(AIC_CHIP_G73X)
     ret = burn_spienc_rotpk();
     if (ret) {
+        efuse_write_disable();
         printf("Error\n");
         return -1;
     }
@@ -411,12 +407,14 @@ int cmd_efuse_do_spienc(int argc, char **argv)
 
     ret = burn_spienc_key_read_write_disable_bits();
     if (ret) {
+        efuse_write_disable();
         printf("Error\n");
         return -1;
     }
 
     ret = burn_jtag_lock_bit();
     if (ret) {
+        efuse_write_disable();
         printf("Error\n");
         return -1;
     }
@@ -424,30 +422,35 @@ int cmd_efuse_do_spienc(int argc, char **argv)
 
     ret = check_brom_spienc_bit();
     if (ret) {
+        efuse_write_disable();
         printf("Error\n");
         return -1;
     }
 
     ret = check_jtag_lock_bit();
     if (ret) {
+        efuse_write_disable();
         printf("Error\n");
         return -1;
     }
     ret = check_spienc_key();
     if (ret) {
+        efuse_write_disable();
         printf("Error\n");
         return -1;
     }
 
     ret = check_spienc_nonce();
     if (ret) {
+        efuse_write_disable();
         printf("Error\n");
         return -1;
     }
 
-#if defined(D13X_BURN_SPIENC_KEY_ENABLE)
+#if defined(AIC_CHIP_D13X) || defined(AIC_CHIP_D21X) || defined(AIC_CHIP_G73X)
     ret = check_spienc_rotpk();
     if (ret) {
+        efuse_write_disable();
         printf("Error\n");
         return -1;
     }
@@ -455,17 +458,21 @@ int cmd_efuse_do_spienc(int argc, char **argv)
 
     ret = check_spienc_key_read_write_disable_bits();
     if (ret) {
+        efuse_write_disable();
         printf("Error\n");
         return -1;
     }
 
+    efuse_write_disable();
     printf("\n");
     printf("Write SPI ENC eFuse done.\n");
-#if defined(DRY_RUN_TO_CONFIRM_KEY_VAL)
+#if defined(AIC_SID_BURN_SIMULATED)
     printf("WARNING: This is a dry run to check the eFuse content, key is not burn to eFuse yet.\n");
 #endif
+#if !defined(AIC_SID_CONTINUE_BOOT_BURN_AFTER)
     while (1)
         continue;
+#endif
     return 0;
 }
 

bsp/examples_bare/test-efuse/efuse_cmds.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
+ * Copyright (c) 2022-2025, ArtInChip Technology Co., Ltd
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -18,9 +18,11 @@ static void cmd_efuse_help(void)
     printf("  efuse help                     : Get this help.\n");
     printf("  efuse dump     offset len      : Dump data from eFuse offset.\n");
     printf("  efuse read     addr offset len : Read eFuse data to RAM addr.\n");
+#ifdef EFUSE_WRITE_SUPPORT
     printf("  efuse write    addr offset len : Write data to eFuse from RAM addr.\n");
     printf("  efuse writehex offset data     : Write data to eFuse from input hex string.\n");
     printf("  efuse writestr offset data     : Write data to eFuse from input string.\n");
+#endif
     printf("  efuse authenticate sjtag key   : Authenticate secure jtag from hex string key.\n");
     printf("  efuse authenticate szone key   : Authenticate secure zone from hex string key.\n");
 }
@@ -82,6 +84,7 @@ static void cmd_efuse_dump(int argc, char **argv)
     printf("\n");
 }
 
+#ifdef EFUSE_WRITE_SUPPORT
 static void cmd_efuse_write(int argc, char **argv)
 {
     ulong addr, offset, len;
@@ -157,6 +160,7 @@ static void cmd_efuse_writestr(int argc, char **argv)
 
     printf("Program efuse done.\n");
 }
+#endif
 
 static void cmd_efuse_authenticate(int argc, char **argv)
 {
@@ -200,18 +204,26 @@ static int cmd_efuse_do(int argc, char **argv)
         cmd_efuse_dump(argc - 1, &argv[1]);
         return 0;
     }
+#ifdef EFUSE_WRITE_SUPPORT
     if (!strcmp(argv[1], "write")) {
+        efuse_write_enable();
         cmd_efuse_write(argc - 1, &argv[1]);
+        efuse_write_disable();
         return 0;
     }
     if (!strcmp(argv[1], "writehex")) {
+        efuse_write_enable();
         cmd_efuse_writehex(argc - 1, &argv[1]);
+        efuse_write_disable();
         return 0;
     }
     if (!strcmp(argv[1], "writestr")) {
+        efuse_write_enable();
         cmd_efuse_writestr(argc - 1, &argv[1]);
+        efuse_write_disable();
         return 0;
     }
+#endif
     if (!strcmp(argv[1], "authenticate")) {
         cmd_efuse_authenticate(argc - 1, &argv[1]);
         return 0;

kernel/common/include/osal/aic_osal.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
+ * Copyright (c) 2022-2025, ArtInChip Technology Co., Ltd
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -161,6 +161,7 @@ static inline void aicos_msleep(uint32_t delay) {}
 
 // memory
 void *aicos_malloc_try_cma(size_t size);
+void *aicos_malloc_align_try_cma(size_t size, size_t align);
 
 #ifdef __cplusplus
  }

kernel/common/osal/aic_osal.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022, ArtInChip Technology Co., Ltd
+ * Copyright (c) 2022-2025, ArtInChip Technology Co., Ltd
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -101,3 +101,22 @@ extern bool lv_drop_one_cached_image();
     return aicos_malloc(MEM_CMA, size);
 #endif
 }
+
+void *aicos_malloc_align_try_cma(size_t size, size_t align)
+{
+#if defined(LPKG_USING_LVGL)
+extern bool lv_drop_one_cached_image();
+    while (1) {
+        void *data = aicos_malloc_align(MEM_CMA, size, align);
+        if (data)
+            return data;
+
+        bool res = lv_drop_one_cached_image();
+        if (res == false) {
+            return NULL;
+        }
+    }
+#else
+    return aicos_malloc_align(MEM_CMA, size, align);
+#endif
+}

packages/artinchip/mpp/base/memory/mpp_mem.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
+ * Copyright (c) 2022-2025, ArtInChip Technology Co., Ltd
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -126,26 +126,33 @@ void show_mem_info_debug()
 }
 
 /***************************** physic memory *****************************************/
-#define ALIGN_1024B(x) ((x+1023)&(~1023))
+#define DEBUG_PHY_MEM (0)
-// base address of reserved buffer
-#define BASE_ADDR 0x43a00000
-#define MEMORY_NUM 48
-//#define USE_CARVOUT
 
+#if DEBUG_PHY_MEM
+#include <pthread.h>
+#define MEMORY_NUM 48
 struct phy_mem_info {
     unsigned int addr;
-    unsigned int align_addr; // 8 bytes align
     int size;
     int used;
 };
-
+static pthread_mutex_t  g_phy_mem_mutex = PTHREAD_MUTEX_INITIALIZER;
 struct phy_mem_info info[MEMORY_NUM];
-unsigned int g_addr = BASE_ADDR;
 int total_cnt = 0;
+#endif
+
 unsigned int mpp_phy_alloc(size_t size)
 {
-    int i;
+    unsigned int addr = (unsigned long)aicos_malloc_align_try_cma(size, 1024);
+    if (addr == 0) {
+        loge("mpp_phy_alloc failed");
+        return 0;
+    }
+    aicos_dcache_clean_invalid_range((unsigned long *)((unsigned long)addr), size);
 
+#if DEBUG_PHY_MEM
+    int i;
+    pthread_mutex_lock(&g_phy_mem_mutex);
     for(i=0; i<MEMORY_NUM; i++) {
         if(info[i].used == 0)
             break;
@@ -153,37 +160,30 @@ unsigned int mpp_phy_alloc(size_t size)
 
     if(i == MEMORY_NUM) {
         loge("memory count exceed max number");
+        pthread_mutex_unlock(&g_phy_mem_mutex);
         return 0;
     }
 
-#ifdef USE_CARVOUT
+    info[i].addr = addr;
-    info[i].addr = g_addr;
-    info[i].align_addr = info[i].addr;
-    info[i].size = ALIGN_1024B(size);
-    g_addr += info[total_cnt].size;
-#else
-    info[i].addr = (unsigned long)aicos_malloc_try_cma(ALIGN_UP(size, CACHE_LINE_SIZE) + 1024);
-    info[i].align_addr = ALIGN_1024B(info[i].addr);
     info[i].size = size;
-#endif
     info[i].used = 1;
     total_cnt ++;
+    pthread_mutex_unlock(&g_phy_mem_mutex);
+#endif
 
-    aicos_dcache_clean_invalid_range((unsigned long *)((unsigned long)info[i].align_addr),
+    logw("mpp_phy_alloc success, addr: %08x, size: %d", addr, (int)size);
-                                     ALIGN_UP(info[i].size, CACHE_LINE_SIZE));
+    return addr;
-
-    logw("mpp_phy_alloc success, addr: %08x, align_addr: %08x, size: %d",
-        info[i].addr, info[i].align_addr, info[i].size);
-    return info[i].align_addr;
 }
 
 void mpp_phy_free(unsigned int addr)
 {
+#if DEBUG_PHY_MEM
     int i;
-
+    pthread_mutex_lock(&g_phy_mem_mutex);
     for(i=0; i<MEMORY_NUM; i++) {
-        if(info[i].align_addr == addr) {
+        if(info[i].addr == addr) {
             if(info[i].used == 0) {
+                pthread_mutex_unlock(&g_phy_mem_mutex);
                 loge("the buffer not alloc, addr: %08x, size: %d", addr, info[i].size);
                 return;
             }
@@ -192,20 +192,17 @@ void mpp_phy_free(unsigned int addr)
     }
 
     if(i == MEMORY_NUM) {
+        pthread_mutex_unlock(&g_phy_mem_mutex);
         loge("not found the addr: %08x, maybe error!", addr);
         return;
     }
 
     info[i].used = 0;
     total_cnt --;
-
+    pthread_mutex_unlock(&g_phy_mem_mutex);
-    if(total_cnt == 0) {
-        logw("reset base address");
-        g_addr = BASE_ADDR;
-    }
-
-#ifndef USE_CARVOUT
-    aicos_free(MEM_CMA, (void*)(unsigned long)info[i].addr);
 #endif
-    logw("phy_free success, addr: %08x, size: %d", info[i].addr, info[i].size);
+
+    aicos_free_align(MEM_CMA, (void*)(unsigned long)addr);
+
+    logw("phy_free success, addr: %08x", addr);
 }