mirror of
https://gitee.com/Vancouver2017/luban-lite.git
synced 2025-12-16 17:18:56 +00:00
443 lines
14 KiB
C
443 lines
14 KiB
C
/*
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* Copyright (C) 2023-2025, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <aic_hal_dsi.h>
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#include <aic_iopoll.h>
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#define DSI_TIMEOUT_US 1000000
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void dsi_set_lane_assign(void *base, u32 ln_assign)
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{
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reg_write(base + DSI_LANE_CFG, ln_assign);
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}
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void dsi_set_lane_polrs(void *base, u32 ln_polrs)
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{
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reg_set_bits(base + DSI_ANA_CFG1,
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DSI_DATA_LANE_POL_MASK, DSI_DATA_LANE_POL(ln_polrs));
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}
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void dsi_set_data_clk_polrs(void *base, u32 dc_inv)
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{
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if (dc_inv)
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reg_set_bit(base + DSI_ANA_CFG1, DSI_DATA_CLK_POL);
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else
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reg_clr_bit(base + DSI_ANA_CFG1, DSI_DATA_CLK_POL);
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}
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void dsi_interrupt_init(void *base, u32 irq1_flag, u32 irq2_flag)
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{
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if (irq1_flag)
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reg_write(base + DSI_IRQ_EN1, irq1_flag);
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if (irq2_flag)
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reg_write(base + DSI_IRQ_EN2, irq2_flag);
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}
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void dsi_dcs_lw(void *base, u32 enable)
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{
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if (enable)
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reg_set_bit(base + DSI_CMD_MODE_CFG, DSI_CMD_MODE_CFG_DCS_LW);
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else
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reg_clr_bit(base + DSI_CMD_MODE_CFG, DSI_CMD_MODE_CFG_DCS_LW);
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}
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void dsi_set_clk_div(void *base, ulong mclk, ulong lp_rate)
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{
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u32 div;
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div = mclk / 8 / lp_rate;
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reg_set_bits(base + DSI_CLK_CFG,
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DSI_CLK_CFG_TO_DIV_MASK | DSI_CLK_CFG_LP_DIV_MASK,
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DSI_CLK_CFG_TO_DIV(div) | DSI_CLK_CFG_LP_DIV(div));
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}
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void dsi_pkg_init(void *base, enum dsi_mode mode)
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{
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reg_set_bits(base + DSI_CTL,
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DSI_CTL_PKG_CFG_CRC_RX_EN | DSI_CTL_PKG_CFG_ECC_RX_EN,
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DSI_CTL_PKG_CFG_CRC_RX_EN | DSI_CTL_PKG_CFG_ECC_RX_EN);
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if (mode & DSI_MOD_NO_EOT_PACKET)
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reg_clr_bit(base + DSI_CTL, DSI_CTL_PKG_CFG_EOTP_TX_EN);
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else
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reg_set_bit(base + DSI_CTL, DSI_CTL_PKG_CFG_EOTP_TX_EN);
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reg_set_bits(base + DSI_DPI_LPTX_TIME,
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DSI_DPI_LPTX_TIME_OUTVACT_MASK | DSI_DPI_LPTX_TIME_INVACT_MASK,
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DSI_DPI_LPTX_TIME_OUTVACT(64) | DSI_DPI_LPTX_TIME_INVACT(64));
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reg_set_bits(base + DSI_TO_CNT_CFG,
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DSI_TO_CNT_CFG_HSTX_MASK | DSI_TO_CNT_CFG_LPRX_MASK,
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DSI_TO_CNT_CFG_HSTX(0) | DSI_TO_CNT_CFG_LPRX(0));
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reg_write(base + DSI_CMD_MODE_CFG,
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DSI_CMD_MODE_CFG_MAX_RD_PKG_SIZE |
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DSI_CMD_MODE_CFG_DCS_LW | DSI_CMD_MODE_CFG_DCS_SR_0P |
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DSI_CMD_MODE_CFG_DCS_SW_1P | DSI_CMD_MODE_CFG_DCS_SW_0P |DSI_CMD_MODE_CFG_GEN_LW | DSI_CMD_MODE_CFG_GEN_SR_2P |
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DSI_CMD_MODE_CFG_GEN_SR_1P | DSI_CMD_MODE_CFG_GEN_SR_0P |
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DSI_CMD_MODE_CFG_GEN_SW_2P | DSI_CMD_MODE_CFG_GEN_SW_1P |
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DSI_CMD_MODE_CFG_GEN_SW_0P);
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}
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static void dsi_dphy_cfg(void *base,
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u32 code, u32 *p_wdata, u32 *p_rdata)
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{
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void *TST1 = base + DSI_PHY_TEST1;
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void *TST2 = base + DSI_PHY_TEST2;
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reg_set_bit(TST2, DSI_PHY_TEST2_EN);
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aic_udelay(1);
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reg_set_bit(TST1, DSI_PHY_TEST1_CLK);
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aic_udelay(1);
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reg_set_bits(TST2, DSI_PHY_TEST2_DIN_MASK, DSI_PHY_TEST2_DIN(code));
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aic_udelay(1);
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reg_clr_bit(TST1, DSI_PHY_TEST1_CLK);
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aic_udelay(1);
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reg_clr_bit(TST2, DSI_PHY_TEST2_EN);
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aic_udelay(1);
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if (p_wdata && p_rdata) {
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u32 *pi = p_wdata;
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u32 *po = p_rdata;
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reg_set_bits(TST2, DSI_PHY_TEST2_DIN_MASK,
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DSI_PHY_TEST2_DIN(*pi++));
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aic_udelay(1);
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reg_set_bit(TST1, DSI_PHY_TEST1_CLK);
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aic_udelay(1);
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*po++ = reg_rd_bits(TST2,
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DSI_PHY_TEST2_DOUT_MASK, DSI_PHY_CFG_LP11_TIME_SHIFT);
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aic_udelay(1);
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reg_clr_bit(TST1, DSI_PHY_TEST1_CLK);
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aic_udelay(1);
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}
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}
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static void dsi_dphy_cfg_hsfreq(void *base, ulong mclk)
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{
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u32 freq_rdata = mclk / 1000000;
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u32 freq_wdata;
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static const struct {
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u32 div;
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u32 value;
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} hs_clk_div[] = {
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{ 89, 0x00 }, { 99, 0x10 }, { 109, 0x20 }, { 129, 0x01 },
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{ 139, 0x11 }, { 149, 0x21 }, { 169, 0x02 }, { 179, 0x12 },
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{ 199, 0x22 }, { 219, 0x03 }, { 239, 0x13 }, { 249, 0x23 },
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{ 269, 0x04 }, { 299, 0x14 }, { 329, 0x05 }, { 359, 0x15 },
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{ 399, 0x25 }, { 449, 0x06 }, { 499, 0x16 }, { 549, 0x07 },
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{ 599, 0x17 }, { 649, 0x08 }, { 699, 0x18 }, { 749, 0x09 },
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{ 799, 0x19 }, { 849, 0x29 }, { 899, 0x39 }, { 949, 0x0a },
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{ 999, 0x1a }, { 1049, 0x2a }, { 1099, 0x3a }, { 1149, 0x0b },
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{ 1199, 0x1b }, { 1249, 0x2b }, { 1299, 0x3b }, { 1349, 0x0c },
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{ 1399, 0x1c }, { 1449, 0x2c }, { 1499, 0x3c },
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};
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u32 i, value = 0;
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for (i = 0; i < ARRAY_SIZE(hs_clk_div); ++i) {
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if (hs_clk_div[i].div >= freq_rdata) {
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value = hs_clk_div[i].value;
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#ifdef AIC_DSI_LEGACY_PACKET_CONFIG
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value = value << 1;
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#endif
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break;
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}
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}
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freq_wdata = value;
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dsi_dphy_cfg(base, 0x44, &freq_wdata, &freq_rdata);
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}
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void dsi_phy_init(void *base, ulong mclk, u32 lane, enum dsi_mode mode)
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{
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void *ANA2 = base + DSI_ANA_CFG2;
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void *CFG = base + DSI_PHY_CFG;
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void *TST1 = base + DSI_PHY_TEST1;
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int ret;
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u32 val;
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reg_write(base + DSI_PHY_RD_TIME, 50);
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reg_set_bits(base + DSI_PHY_CLK_TIME,
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DSI_PHY_CLK_TIME_HS2LP_MASK | DSI_PHY_CLK_TIME_LP2HS_MASK,
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DSI_PHY_CLK_TIME_HS2LP(20) | DSI_PHY_CLK_TIME_LP2HS(20));
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reg_set_bits(base + DSI_PHY_DATA_TIME,
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DSI_PHY_DATA_TIME_HS2LP_MASK | DSI_PHY_DATA_TIME_LP2HS_MASK,
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DSI_PHY_DATA_TIME_HS2LP(20) | DSI_PHY_DATA_TIME_LP2HS(20));
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reg_set_bit(ANA2, DSI_ANA_CFG2_EN_BIAS);
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aic_udelay(5);
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reg_set_bits(ANA2, DSI_ANA_CFG2_EN_VP_MASK, DSI_ANA_CFG2_EN_VP(3));
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reg_set_bits(ANA2, DSI_ANA_CFG2_EN_LDO_MASK,
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DSI_ANA_CFG2_EN_LDO(0x1F));
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aic_udelay(10);
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reg_set_bit(ANA2, DSI_ANA_CFG2_EN_RESCAL);
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reg_set_bit(ANA2, DSI_ANA_CFG2_ON_RESCAL);
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ret = readl_poll_timeout(ANA2, val, val & DSI_ANA_CFG2_RCAL_FLAG,
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DSI_TIMEOUT_US);
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if (ret) {
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pr_err("Timeout during wait rcal flag\n");
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return;
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}
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reg_set_bit(ANA2, DSI_ANA_CFG2_EN_CLK);
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reg_set_bit(TST1, DSI_PHY_TEST1_CLR);
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aic_udelay(5);
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reg_clr_bit(CFG, DSI_PHY_CFG_RST_RSTN);
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aic_udelay(5);
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reg_clr_bit(CFG, DSI_PHY_CFG_RST_SHUTDOWNZ);
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aic_udelay(5);
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reg_clr_bit(TST1, DSI_PHY_TEST1_CLR);
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aic_udelay(5);
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dsi_dphy_cfg_hsfreq(base, mclk);
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dsi_dphy_cfg(base, 0, NULL, NULL);
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reg_set_bit(CFG, DSI_PHY_CFG_RST_SHUTDOWNZ);
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aic_udelay(5);
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reg_set_bit(CFG, DSI_PHY_CFG_RST_RSTN);
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aic_udelay(5);
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reg_set_bits(CFG, DSI_PHY_CFG_LP11_TIME_MASK,
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DSI_PHY_CFG_LP11_TIME(10));
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reg_set_bits(CFG, DSI_PHY_CFG_DATA_LANE_MASK,
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DSI_PHY_CFG_DATA_LANE(lane - 1));
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aic_udelay(5);
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if (mode & DSI_CLOCK_NON_CONTINUOUS) {
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reg_clr_bit(CFG, DSI_PHY_CFG_HSCLK_REQ);
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aic_udelay(5);
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reg_set_bit(CFG, DSI_PHY_CFG_AUTO_CLK_EN);
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aic_udelay(5);
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}
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reg_set_bit(CFG, DSI_PHY_CFG_RST_CLK_EN);
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}
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void dsi_hs_clk(void *base, u32 enable)
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{
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int ret;
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u32 val;
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if (enable) {
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ret = readl_poll_timeout(base + DSI_PHY_STA,
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val, val & DSI_PHY_STA_STOP_STATE_C,
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DSI_TIMEOUT_US);
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if (ret) {
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pr_err("Timeout during wait phy stop state c\n");
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return;
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}
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reg_set_bit(base + DSI_PHY_CFG, DSI_PHY_CFG_HSCLK_REQ);
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return;
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}
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reg_clr_bit(base + DSI_PHY_CFG, DSI_PHY_CFG_HSCLK_REQ);
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ret = readl_poll_timeout(base + DSI_PHY_STA,
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val, val & DSI_PHY_STA_STOP_STATE_C,
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DSI_TIMEOUT_US);
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if (ret)
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pr_err("Timeout during wait phy stop state c\n");
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}
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void dsi_set_vm(void *base, enum dsi_mode mode, enum dsi_format format,
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u32 lane, u32 vc, const struct display_timing *timing)
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{
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void *IFCFG = base + DSI_DPI_IF_CFG;
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void *INFMT = base + DSI_DPI_IN_FMT;
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void *INPOL = base + DSI_DPI_IN_POL;
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void *CMDCFG = base + DSI_CMD_MODE_CFG;
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void *VIDCFG = base + DSI_VID_MODE_CFG;
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u32 if_cfg_fmt[] = {0, 0, 1, 2};
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u32 in_fmt_dt[] = {5, 3, 3, 1};
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u32 dsi_bits_per_pixel[] = {24, 24, 18, 16};
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u32 ht = timing->hback_porch + timing->hsync_len + timing->hactive +
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timing->hfront_porch;
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if (unlikely(format >= DSI_FMT_MAX))
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BUG();
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reg_clr_bit(IFCFG, DSI_DPI_IF_CFG_SHUTD);
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reg_clr_bit(IFCFG, DSI_DPI_IF_CFG_COLORM);
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reg_set_bits(IFCFG, DSI_DPI_IF_CFG_FMT_MASK,
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DSI_DPI_IF_CFG_FMT(if_cfg_fmt[format]));
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reg_set_bits(INFMT, DSI_DPI_IN_FMT_DT_MASK,
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DSI_DPI_IN_FMT_DT(in_fmt_dt[format]));
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if (format == DSI_FMT_RGB666L)
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reg_set_bit(INFMT, DSI_DPI_IN_FMT_LOOSELY18);
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else
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reg_clr_bit(INFMT, DSI_DPI_IN_FMT_LOOSELY18);
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reg_set_bits(base + DSI_DPI_VC, DSI_DPI_VC_NUM_MASK,
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DSI_DPI_VC_NUM(vc));
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reg_clr_bit(INPOL, DSI_DPI_IN_POL_DE);
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reg_set_bit(INPOL, DSI_DPI_IN_POL_VSYNC);
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reg_set_bit(INPOL, DSI_DPI_IN_POL_HSYNC);
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reg_clr_bit(INPOL, DSI_DPI_IN_POL_SHUTDOWN);
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reg_clr_bit(INPOL, DSI_DPI_IN_POL_COLORM);
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if (mode & DSI_MOD_CMD_MODE) {
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reg_set_bit(base + DSI_CTL, DSI_CTL_DSI_MODE);
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reg_write(base + DSI_EDPI_CMD_SIZE, timing->hactive);
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reg_clr_bit(CMDCFG, DSI_CMD_MODE_CFG_ACK_REQ_EN);
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reg_clr_bit(CMDCFG, DSI_CMD_MODE_CFG_TE_EN);
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reg_clr_bit(CMDCFG, DSI_CMD_MODE_CFG_DCS_LW);
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return;
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}
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reg_clr_bit(base + DSI_CTL, DSI_CTL_DSI_MODE);
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reg_set_bits(VIDCFG, DSI_VID_MODE_CFG_TYPE_MASK,
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DSI_VID_MODE_CFG_TYPE(mode));
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reg_set_bit(VIDCFG, DSI_VID_MODE_CFG_LP_EN_VSA);
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reg_set_bit(VIDCFG, DSI_VID_MODE_CFG_LP_EN_VBP);
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reg_set_bit(VIDCFG, DSI_VID_MODE_CFG_LP_EN_VFP);
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reg_set_bit(VIDCFG, DSI_VID_MODE_CFG_LP_EN_VACT);
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reg_set_bit(VIDCFG, DSI_VID_MODE_CFG_LP_EN_HBP);
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if (mode & DSI_MOD_VID_BURST)
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reg_set_bit(VIDCFG, DSI_VID_MODE_CFG_LP_EN_HFP);
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else
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reg_clr_bit(VIDCFG, DSI_VID_MODE_CFG_LP_EN_HFP);
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reg_clr_bit(VIDCFG, DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN);
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reg_set_bit(VIDCFG, DSI_VID_MODE_CFG_CMD_LPTX_FORCE);
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reg_write(base + DSI_VID_PKG_SIZE, timing->hactive);
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reg_write(base + DSI_VID_CHK_NUM, 1);
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reg_write(base + DSI_VID_NULL_SIZE, 0);
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reg_set_bits(base + DSI_VID_HINACT_TIME,
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DSI_VID_HSA_TIME_MASK,
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DSI_VID_HSA_TIME(
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timing->hsync_len * dsi_bits_per_pixel[format]/(8 * lane)));
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reg_set_bits(base + DSI_VID_HINACT_TIME,
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DSI_VID_HBP_TIME_MASK,
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DSI_VID_HBP_TIME(
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timing->hback_porch *
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dsi_bits_per_pixel[format]/(8 * lane)));
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reg_write(base + DSI_VID_HT_TIME,
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ht * dsi_bits_per_pixel[format]/(8 * lane));
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reg_set_bits(base + DSI_VID_VACT_LINE,
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DSI_VID_VSA_LINE_MASK,
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DSI_VID_VSA_LINE(timing->vsync_len));
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reg_set_bits(base + DSI_VID_VBLANK_LINE,
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DSI_VID_VBP_TIME_MASK,
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DSI_VID_VBP_TIME(timing->vback_porch));
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reg_set_bits(base + DSI_VID_VBLANK_LINE,
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DSI_VID_VFP_LINE_MASK,
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DSI_VID_VFP_LINE(timing->vfront_porch));
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reg_set_bits(base + DSI_VID_VACT_LINE,
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DSI_VID_VACT_TIME_MASK,
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DSI_VID_VACT_TIME(timing->vactive));
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}
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void dsi_cmd_wr(void *base, u32 dt, u32 vc, const u8 *data, u32 len)
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{
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const u8 *p = data;
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u8 d0, d1, i;
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u32 val;
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int ret;
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void *CMDCFG = base + DSI_CMD_MODE_CFG;
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switch (dt) {
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case DSI_DT_GEN_WR_P0:
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case DSI_DT_GEN_RD_P0:
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d0 = 0; d1 = 0; i = 0;
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break;
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case DSI_DT_GEN_WR_P1:
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case DSI_DT_GEN_RD_P1:
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case DSI_DT_DCS_WR_P0:
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case DSI_DT_DCS_RD_P0:
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d0 = *p++; d1 = 0; i = 1;
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break;
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case DSI_DT_GEN_WR_P2:
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case DSI_DT_GEN_RD_P2:
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case DSI_DT_DCS_WR_P1:
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d0 = *p++; d1 = *p++; i = 2;
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break;
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case DSI_DT_GEN_LONG_WR:
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case DSI_DT_DCS_LONG_WR:
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d0 = len >> 0; d1 = (len >> 8) & 0xff; i = 0;
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break;
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default:
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d0 = 0; d1 = 0; i = 0;
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break;
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}
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switch (dt) {
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case DSI_DT_GEN_WR_P0:
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reg_set_bit(CMDCFG, DSI_CMD_MODE_CFG_GEN_SW_0P);
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break;
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case DSI_DT_GEN_WR_P1:
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reg_set_bit(CMDCFG, DSI_CMD_MODE_CFG_GEN_SW_1P);
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break;
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case DSI_DT_GEN_WR_P2:
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reg_set_bit(CMDCFG, DSI_CMD_MODE_CFG_GEN_SW_2P);
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break;
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case DSI_DT_GEN_RD_P0:
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reg_set_bit(CMDCFG, DSI_CMD_MODE_CFG_GEN_SR_0P);
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break;
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case DSI_DT_GEN_RD_P1:
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reg_set_bit(CMDCFG, DSI_CMD_MODE_CFG_GEN_SR_1P);
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break;
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case DSI_DT_GEN_RD_P2:
|
|
reg_set_bit(CMDCFG, DSI_CMD_MODE_CFG_GEN_SR_2P);
|
|
break;
|
|
case DSI_DT_GEN_LONG_WR:
|
|
reg_set_bit(CMDCFG, DSI_CMD_MODE_CFG_GEN_LW);
|
|
break;
|
|
case DSI_DT_DCS_WR_P0:
|
|
reg_set_bit(CMDCFG, DSI_CMD_MODE_CFG_DCS_SW_0P);
|
|
break;
|
|
case DSI_DT_DCS_WR_P1:
|
|
reg_set_bit(CMDCFG, DSI_CMD_MODE_CFG_DCS_SW_1P);
|
|
break;
|
|
case DSI_DT_DCS_RD_P0:
|
|
reg_set_bit(CMDCFG, DSI_CMD_MODE_CFG_DCS_SR_0P);
|
|
break;
|
|
case DSI_DT_DCS_LONG_WR:
|
|
reg_set_bit(CMDCFG, DSI_CMD_MODE_CFG_DCS_LW);
|
|
break;
|
|
}
|
|
|
|
if (dt == DSI_DT_GEN_RD_P0 || dt == DSI_DT_GEN_RD_P1 ||
|
|
dt == DSI_DT_GEN_RD_P2 || dt == DSI_DT_DCS_RD_P0) {
|
|
reg_clr_bit(CMDCFG, DSI_CMD_MODE_CFG_ACK_REQ_EN);
|
|
reg_set_bit(base + DSI_CTL, DSI_CTL_PKG_CFG_BTA_EN);
|
|
} else {
|
|
reg_clr_bit(CMDCFG, DSI_CMD_MODE_CFG_ACK_REQ_EN);
|
|
reg_clr_bit(base + DSI_CTL, DSI_CTL_PKG_CFG_BTA_EN);
|
|
}
|
|
|
|
for (; i < len; i += 4)
|
|
reg_write(base + DSI_GEN_PD_CFG,
|
|
(*(p + i + 3) << 24) | (*(p + i + 2) << 16) |
|
|
(*(p + i + 1) << 8) | (*(p + i + 0) << 0));
|
|
|
|
ret = readl_poll_timeout(base + DSI_PHY_STA,
|
|
val, val & DSI_PHY_STA_STOP_STATE_0,
|
|
DSI_TIMEOUT_US);
|
|
if (ret) {
|
|
pr_err("Timeout during wait phy stop state 0\n");
|
|
return;
|
|
}
|
|
|
|
reg_write(base + DSI_GEN_PH_CFG,
|
|
(d1 << 16) | (d0 << 8) | (vc << 6) | dt);
|
|
|
|
ret = readl_poll_timeout(base + DSI_CMD_PKG_STA,
|
|
val, val & DSI_CMD_PKG_STA_PLD_W_EMPTY,
|
|
DSI_TIMEOUT_US);
|
|
if (ret) {
|
|
pr_err("failed to write pld write fifo\n");
|
|
return;
|
|
}
|
|
|
|
aic_udelay(10);
|
|
}
|
|
|