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324 lines
8.0 KiB
C
324 lines
8.0 KiB
C
/*
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* Copyright (c) 2022-2025, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Authors: Li Siyao <siyao.li@artinchip.com>
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*/
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#include "aic_core.h"
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#include "hal_psadc.h"
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#include <string.h>
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/* Register definition of PSADC Controller */
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#define PSADC_MCR 0x000
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#define PSADC_TCR 0x004
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#define PSADC_NODE1 0x008
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#define PSADC_NODE2 0x00C
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#define PSADC_MSR 0x010
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#define PSADC_CALCSR 0x014
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#define PSADC_FILTER 0x01C
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#define PSADC_Q1FCR 0x020
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#define PSADC_Q2FCR 0x024
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#define PSADC_Q1FDR 0x040
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#define PSADC_Q2FDR 0x080
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#define PSADC_VERSION 0xFFC
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#define PSADC_MCR_Q1_TRIGS BIT(22)
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#define PSADC_MCR_Q1_TRIGA BIT(20)
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#define PSADC_MCR_Q1_INTE BIT(18)
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#define PSADC_MCR_QUE_COMB BIT(1)
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#define PSADC_MCR_EN BIT(0)
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#define PSADC_TCR_Q2_TRIG_CNT_SHIFT 4
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#define PSADC_QX_NODE_MASK 4
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#define PSADC_MSR_QX_CNT_MASK GENMASK(27, 24)
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#define PSADC_MSR_Q2_FERR BIT(6)
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#define PSADC_MSR_Q2_INT BIT(4)
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#define PSADC_MSR_Q1_FERR BIT(2)
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#define PSADC_MSR_Q1_INT BIT(0)
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#define PSADC_FCR_DCNT_MASK GENMASK(28, 24)
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#define PSADC_FCR_DCNT_SHIFT 24
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#define PSADC_FCR_DRTH_SHIFT 8
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#define PSADC_FCR_UF_STS BIT(17)
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#define PSADC_FCR_OF_STS BIT(16)
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#define PSADC_FCR_FIFO_ERRIE BIT(3)
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#define PSADC_FCR_FIFO_DRQE BIT(2)
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#define PSADC_FCR_FIFO_RDYIE BIT(1)
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#define PSADC_FCR_FIFO_FLUSH BIT(0)
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#define PSADC_Q1FDR_CHNUM_SHIFT 12
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#define PSADC_Q1FDR_CHNUM_MASK GENMASK(15, 12)
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#define PSADC_Q1FDR_DATA_MASK GENMASK(11, 0)
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#define PSADC_Q1FDR_DATA BIT(0)
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#define PSADC_Q2FDR_CHNUM_SHIFT 12
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#define PSADC_Q2FDR_CHNUM_MASK GENMASK(15, 12)
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#define PSADC_Q2FDR_DATA_MASK GENMASK(11, 0)
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#define PSADC_Q2FDR_DATA BIT(0)
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extern struct aic_psadc_ch aic_psadc_chs[];
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extern struct aic_psadc_queue aic_psadc_queues[];
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static u32 g_psadc_ch_num = 0; // the number of available channel
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static u32 g_psadc_ch_data[AIC_PSADC_CH_NUM] = {0};
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static inline void psadc_writel(u32 val, int reg)
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{
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writel(val, PSADC_BASE + reg);
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}
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static inline u32 psadc_readl(int reg)
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{
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return readl(PSADC_BASE + reg);
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}
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static void psadc_reg_enable(int offset, int bit, int enable)
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{
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int tmp = psadc_readl(offset);
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if (enable)
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tmp |= bit;
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else
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tmp &= ~bit;
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psadc_writel(tmp, offset);
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}
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void hal_psadc_enable(int enable)
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{
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psadc_reg_enable(PSADC_MCR, PSADC_MCR_EN, enable);
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}
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void hal_psadc_single_queue_mode(int enable)
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{
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psadc_reg_enable(PSADC_MCR, PSADC_MCR_QUE_COMB, enable);
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}
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void hal_psadc_qc_irq_enable(bool enable)
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{
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#ifdef AIC_PSADC_TRIG_BY_EPWM
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psadc_reg_enable(PSADC_MCR, PSADC_MCR_Q1_TRIGA, enable);
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#endif
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psadc_reg_enable(PSADC_MCR, PSADC_MCR_Q1_INTE, enable);
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}
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static void psadc_fifo1_flush(void)
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{
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u32 val = psadc_readl(PSADC_Q1FCR);
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if (val & PSADC_FCR_UF_STS)
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pr_err("FIFO is Underflow! FCR: 0x%#x\n", val);
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if (val & PSADC_FCR_OF_STS)
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pr_err("FIFO is Overflow! FCR: 0x%#x\n", val);
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psadc_writel(val | PSADC_FCR_FIFO_FLUSH, PSADC_Q1FCR);
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}
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static void psadc_fifo_init(void)
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{
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u32 val = PSADC_FCR_FIFO_ERRIE | PSADC_FCR_FIFO_RDYIE;
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val |= g_psadc_ch_num << PSADC_FCR_DRTH_SHIFT;
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psadc_writel(val, PSADC_Q1FCR);
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psadc_writel(val, PSADC_Q2FCR);
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}
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int hal_psadc_set_queue_node(int queue, int ch, int node_ordinal)
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{
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int val;
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int node_chan = 0;
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u32 node_regs = 0;
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if (queue == AIC_PSADC_Q1)
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node_regs = PSADC_NODE1;
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if (queue == AIC_PSADC_Q2)
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node_regs = PSADC_NODE2;
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node_chan = ch << (node_ordinal * PSADC_QX_NODE_MASK);
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val = psadc_readl(node_regs);
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val |= node_chan;
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psadc_writel(val, node_regs);
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return 0;
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}
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int hal_psadc_ch_init(void)
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{
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int val = 0;
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struct aic_psadc_queue *queue = &aic_psadc_queues[AIC_PSADC_QC];
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psadc_fifo_init();
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if (queue->type == AIC_PSADC_QC) {
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val = queue->nodes_num - 1;
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psadc_writel(val, PSADC_TCR);
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}
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hal_psadc_qc_irq_enable(true);
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return 0;
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}
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void aich_psadc_status_show(void)
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{
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int version = psadc_readl(PSADC_VERSION);
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printf("In PSADC V%s, trigger source: %s\n", EXPAND_BCD_VER(version),
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#ifdef AIC_PSADC_TRIG_BY_EPWM
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"EPWM"
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#else
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"software"
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#endif
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);
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printf("Enabled %d channels: ", g_psadc_ch_num);
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for (int i = 0; i < g_psadc_ch_num; i++) {
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if (aic_psadc_chs[i].available)
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printf("[%d] ", aic_psadc_chs[i].id);
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}
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printf("\n");
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return;
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}
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static void psadc_read_ch(int cnt)
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{
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u32 data;
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int val;
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val = psadc_readl(PSADC_Q1FDR);
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data = val & PSADC_Q1FDR_DATA_MASK;
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g_psadc_ch_data[cnt] = data;
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pr_debug("[%d]: ADC value %d\n", cnt, val);
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}
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struct aic_psadc_ch *hal_psadc_ch_is_valid(u32 ch)
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{
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s32 i;
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if (ch >= AIC_PSADC_CH_NUM) {
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pr_err("Invalid channel %d\n", ch);
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return NULL;
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}
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for (i = 0; i < g_psadc_ch_num; i++) {
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if (aic_psadc_chs[i].id != ch)
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continue;
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if (aic_psadc_chs[i].available)
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return &aic_psadc_chs[i];
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else
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break;
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}
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pr_debug("Ch%d is unavailable!\n", ch);
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return NULL;
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}
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int hal_psadc_read(u32 *val, u32 timeout)
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{
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int ret = 0;
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struct aic_psadc_queue *queue = &aic_psadc_queues[AIC_PSADC_QC];
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RT_ASSERT(queue->complete != NULL);
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#ifdef AIC_PSADC_TRIG_BY_SOFT
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psadc_fifo1_flush();
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psadc_reg_enable(PSADC_MCR, PSADC_MCR_Q1_TRIGS, 1);
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#endif
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ret = aicos_sem_take(queue->complete, timeout);
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if (ret < 0) {
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hal_log_err("Queue%d read timeout!\n", queue->id);
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hal_psadc_qc_irq_enable(false);
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return -ETIMEDOUT;
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}
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if (val) {
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unsigned long state;
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aicos_local_irq_save(&state);
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memcpy(val, g_psadc_ch_data, sizeof(u32) * queue->nodes_num);
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aicos_local_irq_restore(state);
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}
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return 0;
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}
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int hal_psadc_read_poll(u32 *val, u32 timeout)
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{
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u32 q_flag = 0;
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int get_data_flag = 0;
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int time_count = 0;
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struct aic_psadc_queue *queue = &aic_psadc_queues[AIC_PSADC_QC];
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#ifdef AIC_PSADC_TRIG_BY_SOFT
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psadc_fifo1_flush();
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psadc_reg_enable(PSADC_MCR, PSADC_MCR_Q1_TRIGS, 1);
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#endif
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while (1) {
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time_count++;
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q_flag = psadc_readl(PSADC_MSR);
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psadc_writel(q_flag, PSADC_MSR);
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if (q_flag & PSADC_MSR_Q1_INT) {
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get_data_flag++;
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for(int i = 0; i < queue->nodes_num; i++)
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psadc_read_ch(i);
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}
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if (q_flag & PSADC_MSR_Q1_FERR)
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psadc_fifo1_flush();
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if (get_data_flag)
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break;
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if (time_count > timeout) {
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hal_psadc_qc_irq_enable(false);
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return -ETIMEDOUT;
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}
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}
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if (val)
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memcpy(val, g_psadc_ch_data, sizeof(u32) * queue->nodes_num);
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return 0;
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}
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irqreturn_t hal_psadc_isr(int irq, void *arg)
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{
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u32 q_flag = 0, fifo_cnt = 0;
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struct aic_psadc_queue *queue = &aic_psadc_queues[AIC_PSADC_QC];
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q_flag = psadc_readl(PSADC_MSR);
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if (q_flag & PSADC_MSR_Q1_INT) {
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fifo_cnt = (psadc_readl(PSADC_Q1FCR) & PSADC_FCR_DCNT_MASK) >> PSADC_FCR_DCNT_SHIFT;
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for (int j = 0; j < fifo_cnt / queue->nodes_num; j++)
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for (int i = 0; i < queue->nodes_num; i++)
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psadc_read_ch(i);
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if ((queue->nodes_num > 1) && (fifo_cnt % queue->nodes_num)) {
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pr_warn("The is data residue in FIFO: %d/%d\n",
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fifo_cnt, queue->nodes_num);
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psadc_fifo1_flush();
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}
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if (queue->complete)
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aicos_sem_give(queue->complete);
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}
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if (q_flag & PSADC_MSR_Q1_FERR)
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psadc_fifo1_flush();
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psadc_writel(q_flag, PSADC_MSR);
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pr_debug("Q flag: 0x%x\n", q_flag);
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return IRQ_HANDLED;
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}
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void hal_psadc_set_ch_num(u32 num)
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{
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if (num >= AIC_PSADC_CH_NUM) {
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pr_err("Channel number %d is out of range\n", num);
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return;
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}
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g_psadc_ch_num = num;
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}
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